Electrically erasable and programmable read only memory with trench structure

• US 5,146,426 A
• Filed: 11/08/1990
• Issued: 09/08/1992
• Est. Priority Date: 11/08/1990
• Status: Expired due to Fees

• Current Assignee: North American Philips Corp. (Koninklijke Philips N.V.)
• Original Assignee: North American Philips Corp. (Koninklijke Philips N.V.)
• Inventors: Kuo, Di-Son, Tsou, Len-Yuan, Mukherjee, Satyendranath
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US07/610,598
• Time in Patent Office: 670 Days
• Field of Search: 365/185, 365/149, 365/218, 357/23.6, 357/54, 357/55
• US Class Current: 257/316
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An Erasable and Programmable Read Only Memory (EEPROM) cell is provided with an insulated control gate and an insulating floating gate formed in a trench in a semiconductor body. A surface-adjoining drain region is provided alongside an upper portion of a sidewall of the trench, while a source region is provided alongside a lower portion of the trench sidewall, with a channel region extending along the sidewall of the trench between the source and drain regions. The EEPROM cell is programmed by hot electron injection through the sidewall of the trench alongside the channel region, and is erased by Fowler Nordhiem tunneling through a corner region in the bottom of the trench by creating a localized high electric field density in the corner region. In this manner, a highly compact, efficient and durable EEPROM cell is obtained.

Claims

1. An Electrically Erasable and Programmable Read Only Memory (EEPROM) cell, which comprises:

a first semiconductor layer of a first conductivity type and having a high doping level;

a second semiconductor layer of said first conductivity type on said first layer and having a lower doping level than that of said first layer, said first and second layers together forming a source region of said EEPROM cell;

a third semiconductor layer of a second conductivity type opposite to that of said first type on said second layer and extending to a surface of said EEPROM cell;

A fourth surface-adjoining highly-doped semiconductor layer of said first conductivity type provided locally in said third layer and forming a drain region of said EEPROM cell;

a trench extending through said third and fourth layers and partially into but not through said second layer;

a channel region located in a portion of said third layer adjacent the sidewall portion of said trench and extending from said second region to said fourth region;

a gate dielectric covering a sidewall and floor of said trench;

a floating gate on said gate dielectric and extending adjacent the sidewall and floor of said trench;

an intergate dielectric covering at least an inner sidewall and floor of said floating gate;

a control gate located on said intergate dielectric and separated from said channel region by said floating gate;

means for causing a localized high electric field density during an erase portion of an operating cycle of said cell across a corner region of said gate dielectric in the area adjacent the intersection of said trench sidewall and floor.

2. An EEPROM cell as in claim 1, wherein said means for causing a localized high electric field density comprises providing said gate dielectric with a localized portion of reduced thickness at said corner region.

3. An EEPROM cell as in claim 2, wherein said localized portion of said gate dielectric has a thickness of between about 30% to 90% of the thickness of the remaining portions of said gate dielectric.

4. An EEPROM cell as in claim 3, wherein the thickness of said localized portion of said gate dielectric is between about 30 angstroms and about 180 angstroms.

5. An EEPROM cell as in claim 2, wherein said localized gate dielectric portion of reduced thickness comprises a rounded outer edge at said corner region.

6. An EEPROM cell as in claim 2, wherein said localized gate dielectric portion of reduced thickness comprises a notched inner edge at said corner region.

7. An EEPROM cell as claimed in claim 2, wherein said localized gate dielectric portion of reduced thickness comprises both a rounded outer edge and a notched inner edge at said corner region.

8. An EEPROM cell comprising a semiconductor body, an insulated control gate and an insulated floating gate formed in a trench in said body, a surface-adjoining drain region alongside an upper portion of a sidewall of said trench, a source region alongside at least a lower portion of the side-wall of said trench, a channel region extending along the sidewall of said trench between said source and drain regions, means for programming said cell through said trench sidewall adjacent said channel region, and means for erasing said cell through a corner region in the bottom of said trench by causing a localized high electric field density in said corner region during operation.

9. An EEPROM cell as in claim 8, wherein said source region and said insulated floating gate are more closely spaced at said corner region than elsewhere along said trench.

10. An EEPROM cell as in claim 8, formed in an array of such cells, wherein said surface-adjoining drain region of said cell extends in a lateral direction to contact the sidewall of at least one adjacent cell, said drain region additionally forming the drain region of said adjacent cell and an interconnection between said cell and said adjacent cell.