Memory error correction system distributed on a high performance multiprocessor bus and method therefor

• US 5,146,461 A
• Filed: 12/22/1989
• Issued: 09/08/1992
• Est. Priority Date: 11/13/1989
• Status: Expired due to Fees

• Current Assignee: Solbourne Computer, Inc.
• Original Assignee: Solbourne Computer, Inc.
• Inventors: Mati, Nicholas P., Duschatko, Douglas E., Herrington, Richard A.
• Primary Examiner(s): Baker, Stephen M.
• Application Number:
  US07/455,640
• Time in Patent Office: 991 Days
• Field of Search: 371/40.2, 371/37.1
• US Class Current: 714/772
• CPC Class Codes: G06F 11/1044 with specific ECC/EDC distribution

Abstract

A distributed error correction circuit for a synchronous high performance multiprocessor bus wherein the memory directly transfers data containing error fields to the multiprocessor bus without performing an error check. Each device, such as a plurality of processors or input/output busses, connected to the multiprocessor bus has error correction circuitry located between the multiprocessor bus and the device to perform error correction while the data is being transferred off the multiprocessor bus and stored in data buffers at the bandwidth of the multiprocessor bus. The error correction circuit detects and corrects data errors caused by the memory or the multiprocessor bus. The stored data is later transferred out of the buffers at the bandwidth of the device. Data from a device is delivered into the device buffers at the bandwidth of the device for later delivery of the data into memory at the bandwidth of the multiprocessor bus. During such transfers, the error correction circuitry generates the error field as the device data is transferred onto the multiprocessor bus.

Claims

1. A memory error correction system for a multiprocessor system, said system having a system bus, a memory directly connected to said bus, said memory containing lines of data and a plurality of bus data circuits connected to said system bus, said bus data circuits selected from the group consisting of one or a plurality of processors or one or a plurality of input/output bus interface circuits, said memory error correction system comprising:

means connected to each of said plurality of bus data circuits and to said system bus for selectively receiving a line of data with an error field from said memory over said system bus at the bandwidth of the bus,

means in said receiving means and receptive of said memory line of data for detecting errors originating either in said memory of during transfer on said system bus in said memory line of data as said memory line of data is being received from said system bus, said detecting means also automatically correcting any detected errors in said memory line of data after said memory line of data is received,

means connected to said detecting means for storing said corrected memory line of data, said receiving means comprising;

a first register having a bit width equal to the bit width of said line of data,

means for detecting errors in a line of data resident in said first register during the transfer time interval for said line of data from said first register to said second register,

means for correcting said errors in said line of data during the time interval when said data is transferred from said second register to said storing means.

2. The system of claim 1 wherein said detecting means detects and corrects the presence of a single bit error in said memory line of data.

3. The system of claim 2 wherein said error field comprises a check bit field and wherein said detecting means further comprises:

means receptive of each said memory line of data for generating a new check bit field,

means connected to said generating means and receptive of said new check bit field for comparing said new check bit field with said received check bit field, said comparing means issuing a syndrome signal based upon said comparison,

means receptive of said syndrome signal from said comparing means for correcting said memory line of data as said memory line of data is stored in said storing means.

4. The system of claim 1 wherein said system bus is synchronous.

5. A memory error correction system for a high performance processor system, said system having a memory directly connected to said system bus, and at least one input/output bus interface, a high performance system bus, said memory error correction system comprising:

means connected to said at least one input/output bus and to said system bus for selectively receiving a block of data from said memory over said system bus at a first bandwidth at least equal to or greater than the bandwidth of said memory, said block of data having a plurality of lines,

means on said receiving means and receptive of said block of data for detecting errors originating in said memory or on said system bus present in said block of data as said block of data is being received from said system bus, said detecting means also correcting any detected errors caused by said memory or said system bus as said block of data is being received,

means connected to said detecting means for storing said corrected block of data,

means connected to said storing means for delivering said stored block of data at a second bandwidth from said storing means to said at least one input/output bus interface, said second bandwidth being less than said first bandwidth, said receiving means comprises;

a first register having a bit width equal to the bit width of a line of data in said block of data,

a second register having a bit width equal to the bit width of said line of data,

means for detecting errors in a line of data resident in said first register during the transfer time interval for said line of data from said first register to said second register,

means for correcting said errors in said line of data when said data is transferred from said second register to said storing means.

6. The system of claim 5 wherein said first bandwidth is at least 128 Mbytes/second and said second bandwidth is less than 40 Mbytes/second.

7. The system of claim 5 wherein the rate of transfer between said first and second registers equals said first bandwidth.

8. The system of claim 5 wherein said detecting means detects and corrects the presence of a single bit error in a line of data in said block of data.

9. The system of claim 8 wherein each line of said block of data has a check bit field and wherein said detecting means further comprises:

means receptive of each said line of said block of data for generating a new check bit field,

means connected to said generating means and receptive of said new check bit field for comparing said new check bit field with said received check bit field, said comparing means issuing a syndrome signal based upon said comparison,

means receptive of said syndrome signal from said comparing means for correcting said line of said block of data as said line is stored in said storing means.

10. A distributed memory error correction system for a high performance multiprocessor system, said system having a multiprocessor bus, a memory directly connected to said multiprocessor bus without an error correction circuit at the output of said memory to said multiprocessor bus, and at least one input/output bus interface circuit, said distributed memory error correction system comprising:

first means connected to said at least one input/output bus interface circuit and to said multiprocessor bus for selectively receiving a block of data from said memory or from one of said processors over said multiprocessor bus at a multiprocessor bus bandwidth at least equal to or greater than the bandwidth of said memory, said block of data having a plurality of data lines with each data line having an error field, said first receiving means being further capable of detecting and correcting errors in said block of data based on said error field as said block of data is being received wherein said first receiving means comprises;

(a) a first register having a bit width equal to the bit width of a line of data in said block of data,

(b) a second register having a bit width equal to the bit width of said line of data,

(c) means for detecting errors in a line of data resident in said first register during the transfer time interval for said line of data from said first register to said second register

means for correcting said errors in said line of data when said data is transferred from said second register,

means connected to said first receiving means for delivering said corrected block of data to said at least one input/output bus interface circuit at the bandwidth of said at least one input/output bus, said input/output bandwidth being less than said memory bandwidth,

second means on each of said plurality of processors and connected to said multiprocessor bus for selectively receiving said block of data containing said error field from said memory or from one of said other processors over said multiprocessor bus at said multiprocessor bus bandwidth, said second receiving means being further capable of detecting and correcting any errors in said block of data based on said error field as said block of data is being received,

means on each of said plurality of processors and connected to said second receiving means for delivering said corrected block of data to each said processor at the bandwidth of said at least one processor.

11. A high performance multiprocessor system, said system comprising:

a synchronous system bus,

a memory directly connected to said synchronous bus without an error correction circuit between the output of said memory and said system bus,

blocks of data stored in said memory, each block of data having a plurality of lines of data and each line of data having a check bit field,

a plurality of processors connected to said system bus,

one or a plurality of input/output buses,

one or a plurality of input/output interfaces, each of said input/output interfaces being connected to an input/output bus and operating at the respective bandwidth of the interconnected input/output bus, and

a plurality of error correction circuits, one of said error correction circuits connection between said system bus and said input/output interface and one of said error correction circuits connected between said system bus and each of said processors, each said error correction circuit comprising;

(a) means receptive of said line of data for detecting errors originating either in said memory or during transfer on said system bus in said line of data as said line of data is being delivered from said system bus, said detecting means automatically correcting any detected errors in said memory line of data after said memory line of data is delivered,

(b) means connected to said detecting means for storing said corrected line of data at the bandwidth of said synchronous system bus, and

(c) means connected to said storing means for transferring said corrected line of data between said storing means and connected processor or input/output circuit at the bandwidth of said connected processor or input/output circuit, said detecting means comprising;

a first register having a bit width equal to the bit width of a line of data,

a second register having a bit width equal to the bit width of said line of data,

means for detecting errors in a line of data resident in said first register during the transfer time interval for said line of data from said first register to said second register,

means for correcting said errors in said line of data when said data is transferred from said second register to said storing means.

12. The system of claim 11 wherein said detecting means detects and corrects the presence of a single bit error in said memory line of data.

13. The system of claim 11 wherein said detecting means further comprises:

means receptive of each said memory line of data for generating a new check bit field,

means connected to said generating means and receptive of said new check bit field for comparing said new check bit field with said received check bit field, said comparing means issuing a syndrome signal based upon said comparison,

means receptive of said syndrome signal from said comparing means for correcting said memory line of data as said line of data is stored in said storing means.