Scalable neural array processor

• US 5,146,543 A
• Filed: 08/05/1991
• Issued: 09/08/1992
• Est. Priority Date: 05/22/1990
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Pechanek, Gerald G., Vassiliadis, Stamatis
• Primary Examiner(s): MacDonald, Allen R.
• Application Number:
  US07/740,355
• Time in Patent Office: 400 Days
• Field of Search: 395/27, 307/201
• US Class Current: 706/41
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: G06N 3/10 Interfaces, programming languages or software development kits, e.g. for simulating neural networks

Abstract

The neural computing paradigm is characterized as a dynamic and highly computationally intensive system typically consisting of input weight multiplications, product summation, neural state calculations, and complete connectivity among the neurons. Herein is described neural network architecture for a Scalable Neural Array Process (SNAP) which uses a unique intercommunication scheme within an array structure that provides high performance for completely connected network models such as the Hopfield model. SNAP'"'"'s packaging and expansion capabilities are addressed, demonstrating SNAP'"'"'s scalability to larger networks. Each neuron of the processor has an input function element, an activity function element, and a communicating adder. The neuron functions with two state modes, a compute state and a communications state. In response to a compute state, the input function element and said activity function generate a neuron value, and the communicating adder is placed in a compute mode and is responsive to the processor compute state. In a communications state a neuron is responsive to a communications state for operating the communicating adder for communicating a neuron value to an input function element.

Claims

1. A scalable neural array processor comprising a plurality of neurons, each neuron including an input function element, an activity function element, and a device functioning as a communicating adder, including:

state means for defining a compute state and a communications state;

selection means for selecting said compute state or said communications state;

in said compute state said neuron has means responsive to said compute state for operating said input function element and said activity function element to generate a neuron value;

said device functioning as a communicating adder is placed in a compute mode and is responsive to said state means in said compute state; and

in said communication state a neuron has means responsive to said communications state for operating said device functional as a communicating adder for communicating said neuron value to said input function element.