High speed image processing computer with overlapping windows-div

• US 5,146,592 A
• Filed: 01/24/1989
• Issued: 09/08/1992
• Est. Priority Date: 09/14/1987
• Status: Expired due to Term

• Current Assignee: GDE Systems, Inc. (The O'Gara Group, Inc.)
• Original Assignee: Visual Information Technologies Incorporated
• Inventors: Stoner, David T., Dipert, Dwight D., Norsworthy, John P., Thompson, Jay A., Corry, Michael K., Pfeiffer, David M., Fontaine, James A.
• Primary Examiner(s): Herndon, Heather R.
• Application Number:
  US07/301,371
• Time in Patent Office: 1,323 Days
• Field of Search: 364/518, 364/521, 340/721, 340/723, 340/798-800, 382/44-48
• US Class Current: 715/807
• CPC Class Codes: G06F 2207/3828 Multigauge devices, i.e. capable of handling packed numbers without unpacking them
• CPC Class Codes: G06F 5/015 having at least two separately controlled shifting levels, e.g. using shifting matrices G06F5/012 takes precedence
• CPC Class Codes: G06F 7/49921 Saturation, i.e. clipping the result to a minimum or maximum value
• CPC Class Codes: G06F 7/49947 Rounding
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00
• CPC Class Codes: G06F 7/57 Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations G06F7/49, G06F7/491 take precedence
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

An image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives memory addresses from the image algorithm processor (66) for coordinating the reading and writing of an image memory (82) using pixel data processed by the parallel image processor set (72). The image memory controller (68) arbitrates memory address request cycles, memory refresh cycles and screen refresh cycles. The image memory (82) includes different planes (84, 86 and 88) associated with red, green and blue pixel data. Associated with each image memory plane is a video processor (106) for converting parallel image data to high speed serial image data. The pixel data output by the video processor (106) is further processed through look-up tables (108) to provide red, green and blue color signals for output to a video monitor (28). Overlay data is stored in an overlay memory plane (90), and is processed by an associated overlay data processor (80) and a video output overlay processor (116). A window clipping circuitry monitors the memory addresses from the image algorithm processor (66) to determined whether one or more pixels of a multi-pixel word are located outside of a window.

Claims

1. An image processing system, comprising:

a memory for storing image data, said memory having a number of storage locations greater than needed for displaying an image on a monitor;

a memory address generation circuit for generating addresses for accessing said memory;

a window defining circuit for defining a window are in said memory corresponding to a viewable area of said monitor;

circuitry for simultaneously writing plural pixels to said memory;

a window clipping circuitry for monitoring the addresses generated by said address generator circuit and operable to determine whether any one of said plural pixels are located outside said window; and

masking circuitry for writing selected bits of desired pixels into said memory without overwriting non-selected bits.

2. The image processing system of claim 1, further including means for moving said window area to different areas in said memory.

3. The image processing system of claim 1, further including means for defining said window having a corner coordinate of X₀, Y₀ and a diagonal corner coordinate of X₁, Y₁ and means for storing said coordinates for comparison with a pixel location defined as having coordinates X, Y.

4. The image processing system of claim 1 wherein masking circuitry comprises circuitry for generating a pixel mask indicating the desired pixels and for generating a bit mask indicating the selected bits within the pixels to mask.

5. The image processing system of claim 4 wherein said circuitry for simultaneously writing comprises circuitry for simultaneously writing a predetermined number of pixels in the memory and wherein said masking circuitry comprises circuitry for generating a pixel mask word having a bit corresponding to each of said predetermined number of pixels.

6. The image processing system of claim 5 wherein each pixel comprises a predetermined number o bits and wherein masking circuitry further comprises circuitry for generating a bit mask word having a bit corresponding to each of said predetermined number of pixel bits.

10. The method of claim 4 and further comprising the step of storing said coordinates for comparison with a pixel location defined as having coordinates X, Y.

7. A method of processing image data comprising the steps of:

storing image data in a memory having a number of storage locations greater than needed for displaying an image on a monitor;

generating addresses for accessing said memory;

defining a window area in said memory corresponding to a viewable are of said monitor;

generating plural pixels for simultaneously writing to said memory;

monitoring the generated addresses and determining whether one or more of the plural pixels are located outside said window; and

writing selected bits of desired pixels into the memory without overwriting nonselected bits.

8. The method of claim 7 and further comprising the step of moving the window area to different area in said memory.

9. The method of claim 7 and further comprising the step of defining a wind having a corner coordinate of X₀, Y₀, and a diagonal corner coordinate of X₁, Y₁.

11. The method of claim 7 wherein said writing step comprises the steps of generating a pixel mask indicating the desired pixels and generating a bit mask indicating which the selected bits to mask within the desired pixels.

12. The method of claim 11 wherein said step of generating plural pixels comprises the step of generating a predetermined number of pixels for writing to the memory and wherein said step of generating a pixel mask word having a bit corresponding to each of said predetermined number of pixels.

13. The method of claim 12 wherein each pixel comprises a predetermined number of bits and wherein said step of generating a bit mask comprises the step of generating a bit mask word having a bit corresponding to each of said predetermined number of pixel bits.