High speed image processing computer with overlapping windows-div
First Claim
1. An image processing system, comprising:
- a memory for storing image data, said memory having a number of storage locations greater than needed for displaying an image on a monitor;
a memory address generation circuit for generating addresses for accessing said memory;
a window defining circuit for defining a window are in said memory corresponding to a viewable area of said monitor;
circuitry for simultaneously writing plural pixels to said memory;
a window clipping circuitry for monitoring the addresses generated by said address generator circuit and operable to determine whether any one of said plural pixels are located outside said window; and
masking circuitry for writing selected bits of desired pixels into said memory without overwriting non-selected bits.
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Accused Products
Abstract
An image processor having an image algorithm processor (66) operating under control of a writable control store (94), and a number of parallel image processors (72) operating under control of instruction words from a writable control store (100). An image memory controller (68) receives memory addresses from the image algorithm processor (66) for coordinating the reading and writing of an image memory (82) using pixel data processed by the parallel image processor set (72). The image memory controller (68) arbitrates memory address request cycles, memory refresh cycles and screen refresh cycles. The image memory (82) includes different planes (84, 86 and 88) associated with red, green and blue pixel data. Associated with each image memory plane is a video processor (106) for converting parallel image data to high speed serial image data. The pixel data output by the video processor (106) is further processed through look-up tables (108) to provide red, green and blue color signals for output to a video monitor (28). Overlay data is stored in an overlay memory plane (90), and is processed by an associated overlay data processor (80) and a video output overlay processor (116). A window clipping circuitry monitors the memory addresses from the image algorithm processor (66) to determined whether one or more pixels of a multi-pixel word are located outside of a window.
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Citations
13 Claims
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1. An image processing system, comprising:
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a memory for storing image data, said memory having a number of storage locations greater than needed for displaying an image on a monitor; a memory address generation circuit for generating addresses for accessing said memory; a window defining circuit for defining a window are in said memory corresponding to a viewable area of said monitor; circuitry for simultaneously writing plural pixels to said memory; a window clipping circuitry for monitoring the addresses generated by said address generator circuit and operable to determine whether any one of said plural pixels are located outside said window; and masking circuitry for writing selected bits of desired pixels into said memory without overwriting non-selected bits. - View Dependent Claims (2, 3, 4, 5, 6, 10)
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7. A method of processing image data comprising the steps of:
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storing image data in a memory having a number of storage locations greater than needed for displaying an image on a monitor; generating addresses for accessing said memory; defining a window area in said memory corresponding to a viewable are of said monitor; generating plural pixels for simultaneously writing to said memory; monitoring the generated addresses and determining whether one or more of the plural pixels are located outside said window; and writing selected bits of desired pixels into the memory without overwriting nonselected bits. - View Dependent Claims (8, 9, 11, 12, 13)
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Specification