Systems for interconnecting and configuring plurality of memory elements by control of mode signals
First Claim
1. An array processing system comprising:
- A. a plurality of processing element means for processing data in response to instructions;
B. a plurality of memory means, corresponding to the number of processing element means, each said memory means for storing data in a plurality of storage locations each identified with a different one of said processing element means, said storage locations addressable by each said processor element means defining the address space for that processor element means; and
C. memory interconnection means connected to all of said processing element means and all of said memory means responsive to address signals defining an address and a mode signal having one of a plurality of conditions for coupling data between said memory means and said processing element means, said memory interconnection means being responsive to a first condition of said mode signal selected from said plurality of conditions for coupling data between each of said processing element means and its identified memory means, and responsive to a second condition of said mode signal selected from said plurality of conditions for coupling data between selected ones of said processing element means and memory means identified with others of said processing element means such that the address space for said selected ones of said processing element means is expanded to include the address space of said other processing element means.
2 Assignments
0 Petitions
Accused Products
Abstract
An array processing system including a plurality of processing elements each including a processor and an associated memory module, the system further including a router network over which each processing element can transfer messages to other random processing elements, a mechanism by which a processor can transmit data to one of four nearest-neighbor processors. In addition, the processing elements are divided into groups each with four processing elements, in which one of the processing elements can access data in the other processing elements'"'"' memory modules. The routing network switches messages in a plurality of switching stages, with each stage connecting to the next stage through communications paths that are divided into groups, each group, in turn being associated with selected address signals. A communications path continuity test circuit associated with each path detects any discontinuity in the communications path and disables the path. Thus, the stage may attempt to transfer a message over another path associated with the same address.
-
Citations
17 Claims
-
1. An array processing system comprising:
-
A. a plurality of processing element means for processing data in response to instructions; B. a plurality of memory means, corresponding to the number of processing element means, each said memory means for storing data in a plurality of storage locations each identified with a different one of said processing element means, said storage locations addressable by each said processor element means defining the address space for that processor element means; and C. memory interconnection means connected to all of said processing element means and all of said memory means responsive to address signals defining an address and a mode signal having one of a plurality of conditions for coupling data between said memory means and said processing element means, said memory interconnection means being responsive to a first condition of said mode signal selected from said plurality of conditions for coupling data between each of said processing element means and its identified memory means, and responsive to a second condition of said mode signal selected from said plurality of conditions for coupling data between selected ones of said processing element means and memory means identified with others of said processing element means such that the address space for said selected ones of said processing element means is expanded to include the address space of said other processing element means. - View Dependent Claims (2, 3, 4, 5, 6, 7, 10, 11, 12, 13)
-
-
8. An array processing system comprising:
-
A. a plurality of processing element means for processing data in response to instructions; B. a plurality of memory means, corresponding to the number of processing element means, each said memory means for storing data in a plurality of storage locations each identified by an address, each memory means being identified with a different one of said processing element means, said storage locations addressable by each said processor element means defining the address space for that processor element means; and C. memory interconnection means connected to all of said processing element means and all of said memory means responsive to address signals defining an address and a mode signal having one of a plurality of conditions for coupling data between said memory means and said processing element means, said memory interconnection means being responsive to a first condition of said mode signal selected from said plurality of conditions for coupling data between each of said processing element means and its identified memory means, and responsive to a second condition of said mode signal selected from said plurality of conditions for coupling data between a selected one of said processing element means and a selected one of said memory means identified with another of said processing element means as determined by the condition of said mode signal such that the address space for said selected processing element means is expanded to include the address space of said other processing element means. - View Dependent Claims (9, 14, 15, 16, 17)
-
Specification