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Systems for interconnecting and configuring plurality of memory elements by control of mode signals

  • US 5,146,606 A
  • Filed: 03/21/1990
  • Issued: 09/08/1992
  • Est. Priority Date: 09/18/1986
  • Status: Expired due to Term
First Claim
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1. An array processing system comprising:

  • A. a plurality of processing element means for processing data in response to instructions;

    B. a plurality of memory means, corresponding to the number of processing element means, each said memory means for storing data in a plurality of storage locations each identified with a different one of said processing element means, said storage locations addressable by each said processor element means defining the address space for that processor element means; and

    C. memory interconnection means connected to all of said processing element means and all of said memory means responsive to address signals defining an address and a mode signal having one of a plurality of conditions for coupling data between said memory means and said processing element means, said memory interconnection means being responsive to a first condition of said mode signal selected from said plurality of conditions for coupling data between each of said processing element means and its identified memory means, and responsive to a second condition of said mode signal selected from said plurality of conditions for coupling data between selected ones of said processing element means and memory means identified with others of said processing element means such that the address space for said selected ones of said processing element means is expanded to include the address space of said other processing element means.

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