Harmonic noise minimization in a radio receiver by selectively optimizing ic's which produce harmonics in the radio's frequency range

• US 5,146,617 A
• Filed: 10/15/1990
• Issued: 09/08/1992
• Est. Priority Date: 10/15/1990
• Status: Expired due to Term

• Current Assignee: Protocol-ip.com, LLC, Seiko Instruments Incorporated (Seiko Group)
• Original Assignee: Seiko Corporation (Seiko Group), Seiko Epson Corporation (Seiko Group)
• Inventors: Moen, Russell R. Jr.
• Primary Examiner(s): Eisenzopf, Reinhard J.
• Assistant Examiner(s): Pham, Chi H.
• Application Number:
  US07/597,834
• Time in Patent Office: 694 Days
• Field of Search: 455/295, 455/296, 455/298, 455/300, 455/308-312, 455/343, 307/263, 307/491, 307/542, 307/572, 340/825.44, 375/99
• US Class Current: 455/310
• CPC Class Codes: G08B 5/228 combined with other devices having a different main function, e.g. watches
• CPC Class Codes: H03K 5/1252 Suppression or limitation of noise or interference specially adapted for transmission systems H04B15/00, H04L25/08
• CPC Class Codes: H04B 1/086 Portable receivers
• CPC Class Codes: H04B 15/04 the interference being caused by substantially sinusoidal oscillations, e.g. in a receiver or in a tape-recorder

Abstract

An electronic circuit, such as the type which may be found in a watch pager receiver, which contains both analog and digital circuitry, includes harmonic noise minimization circuitry. The minimization circuitry is constructed using standard cell designs which are optimized for particular clock operations. Select circuit components are optimized to produce minimal harmonics, to operate at the predetermined frequency and include resistance means to provide an output of a second known level which is characterized by an optimized output signal having a ramped wave configuration. The optimized output signal is of adequate strength to provide an input to a downstream component.

Claims

1. An electronic circuit having harmonic noise minimization circuitry and downstream circuits which require signals of a first signal level comprising:

at least one clock providing a clock output for timing circuit functions which operates at a known, harmonic-producing predetermined frequency;

a first plurality of digital circuit components having outputs connected to said downstream circuits, and which operate at a frequency other than said predetermined frequency,

a second plurality of digital circuit components also having outputs connected to said downstream circuits, and which operate at said predetermined frequency, and

a power supply which supplies a first supply voltage to said first plurality of digital circuit components, which results in a component output of a first signal level characterized by a substantially square wave signal, which signal is more than the magnitude of said first signal level required by said downstream circuits,

means providing said first supply voltage to said second plurality of digital circuit components,

said second plurality of digital circuits being designed to produce minimal harmonics, to operate at said predetermined frequency and said second plurality of digital circuits including resistance means to provide an output of a second signal level characterized by an output signal having a ramped wave configuration, which output signal has a magnitude not greater than said first signal level required by said downstream circuits.

2. The minimization circuitry of claim 1 wherein said resistance means includes a gate in a CMOS device of reduced width to reduce said first supply voltage input whereby the output of said second plurality of circuits is reduced.

3. A digital electronic circuit as part of a radio/pager receiver, electronic signals at certain interfering frequencies interfering with the operation of said radio/pager receiver, said digital electronic circuit having harmonic noise minimization circuitry comprising:

a plurality of clock mechanisms in a digital circuit, at least one of said clock mechanisms operating at a frequency which generates harmonic signals which normally interfere with the operation of the radio receiver,

a power supply which supplies a known voltage to said electronic circuit,

an array of digital electronic devices coupled to said plurality of clock mechanisms, said array having devices of a first design and devices of a second design, said devices of said first design being standard devices, said devices of said second design being driven by said at least one clock mechanism which operates at an interfering frequency, said devices of said second design being modified to operate at a voltage and current less than said known voltage and current.

4. The circuit of claim 3 wherein said devices of a second design include resistance means having a gate in a CMOS device of reduced width to reduce the voltage output of said devices of a second design.