ECL to CMOS translation and latch logic circuit

• US 5,148,061 A
• Filed: 02/27/1991
• Issued: 09/15/1992
• Est. Priority Date: 02/27/1991
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Hsueh, Paul, Smith, Douglas, Hershkowitz, Gerald B.
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): ROSEEN, RICHARD R
• Application Number:
  US07/661,152
• Time in Patent Office: 566 Days
• Field of Search: 307/451, 307/475, 307/455, 307/480, 307/481
• US Class Current: 326/66
• CPC Class Codes: H03K 3/356043 with synchronous operation
• CPC Class Codes: H03K 3/356139 with synchronous operation

Abstract

A logic circuit that is responsive to applied ECL input logic signals for providing complementary CMOS logic output signals at first and second outputs includes a translation and latch circuit as well as feedback circuitry. The logic circuit includes an input buffer circuit that provides ECL differential logic signals to the translation and latch circuit, the latter of which receives a CMOS clocking pulse. The translation and latch circuit is responsive both to the clocking pulse and the differential ECL logic output signals for producing complementary CMOS control signals at first and second outputs which are latched during the duration of the clocking pulse. A feedback circuit comprising a pair of CMOS inverters each coupled respectively to the first and second outputs of the translation and latch circuit provide feedback control signals which are applied respectively to a pair of CMOS output buffer stages in conjunction with the CMOS control signals to produce the CMOS logic output signals. Between clocking pulses the feedback circuit latches the output signals from the pair of output buffer stages.

Claims

1. A logic circuit for providing translation of input ECL logic signals to CMOS logic output signals, comprising:

input buffer means responsive to applied ECL logic signals for providing differential ECL logic output signals at first and second outputs;

translation and latch circuit means responsive to said differential ECL logic signals and being responsive to clock pulses applied thereto for providing first and second complementary CMOS control signals at respective outputs, said translation and latch circuit means maintaining said first and second CMOS control signals at a predetermined logic level in the absence of said clock pulses;

inverter circuit means responsive to said second CMOS control signal for providing at least one control signal; and

at least one output buffer stage responsive to said first CMOS control signal for providing the CMOS logic output signals at a first output of the logic circuit during said clock pulses and being responsive to said at least one control signal for maintaining the particular logic level of the CMOS logic output signals provided at the output of the logic circuit between clock pulses.

2. The logic circuit of claim 16 including:

said inverter circuit means being responsive to said first CMOS control signal for providing an additional control signal; and

an additional output buffer stage responsive to said second CMOS control signal for providing CMOS logic output signals at a second output of the circuit wherein said CMOS logic output signals appearing at said second output are the complements of said CMOS logic output signals appearing at said first output of the circuit, said additional output buffer stage being responsive to said additional control signal for maintaining the particular logic level of the CMOS logic output signals at said second output of the circuit.

3. The logic circuit of claim 2 wherein said translation and latch circuit means includes:

a translation circuit comprising a first and a second field effect transistor (FET) of like conductivity type each having a gate, source and drain, said gates of said first and second FETs being coupled to said first and second outputs of said input buffer means respectively, said drains being coupled respectively to said first second and first outputs of said translation and latch circuit means; and

current means coupled to said to said sources of said first and second FETs and being responsive to said clock pulses applied at an input thereto for sinking a substantially constant current.

4. The logic circuit of claim 3 wherein said translation and latch circuit means includes a latch circuit, said latch circuit comprising:

a third FET of like conductivity type as said first FET and having a gate, drain and source, said source being coupled to said drain of said first FET, said drain being coupled to said second output and said gate being coupled to said first output;

a fourth FET of like conductivity type as said second FET and having a gate, drain and source, said source being coupled to said drain of said second FET, said drain being coupled to said first output and said gate being coupled to said second output;

a fifth and sixth FET of a second conductivity type each having a gate, drain and source, said sources being coupled to said second output and said drains being coupled to a first power supply conductor, said gate of said fifth FET being coupled to said input to which said clock pulse is applied and said gate of said sixth FET being coupled to said first output; and

a seventh and eighth FET of said second conductivity type each having a gate, drain and source, said sources being coupled to said first output, said drains being coupled to said first power supply conductor, said gate of said seventh FET being coupled to said input to which said clock pulse is applied and said gate of said eighth FET being coupled to said second output.

5. The logic circuit of claim 4 wherein said at least one output buffer stage includes:

a ninth FET of said second conductivity type having a gate, drain and source, said gate being coupled to said first output of the translation and latch circuit means, said drain being coupled to said first power supply conductor and said source being coupled to said first output of the circuit; and

a tenth FET of said first conductivity type having a gate, drain and source, said gate being coupled to said inverter circuit means for receiving said at least one control signal, said drain being coupled to said first output of the circuit and said source being coupled to a second power supply conductor.

6. The logic circuit of claim 5 wherein said additional output buffer stage includes:

an eleventh FET of said second conductivity type having a gate, drain and source, said gate being coupled to said second output of the translation and latch circuit means, said drain being coupled to said first power supply conductor and said source being coupled to said second output of the circuit; and

a twelfth FET of said first conductivity type having a gate, drain and source, said gate being coupled to said inverter circuit means for receiving said additional control signal, said drain being coupled to said second output of the circuit and said source being coupled to said second power supply conductor.

7. The logic circuit of claim 6 wherein said inverter circuit means includes:

a first inverter having an input coupled to said second output of the translation and latch circuit means and an output, said first inverter being responsive to said second CMOS control signal for providing said at least one control signal at said output thereof; and

a second inverter having an input coupled to said first output of said translation and latch circuit means and an output, said second inverter being responsive to said first CMOS control signal for providing said additional control signal at said output thereof.

8. An integrated logic circuit responsive to applied ECL input logic signals for providing CMOS output logic signals, comprising:

input buffer means responsive to the ECL input logic signals for providing differential ECL logic output signals;

circuit means responsive both to applied clock pulses and said differential ECL logic output signals for providing first and second CMOS control signals at first and second outputs thereof and for latching said first and second CMOS control signals to a predetermined logic level between said applied pulses;

inverter circuit means responsive to said first and second CMOS control signals for providing first and second complementary control signals; and

output circuit means responsive to said first and second CMOS control signals and said first and second control signals for providing complementary CMOS output logic signals at first and second outputs of the logic circuit, said inverter circuit means causing said CMOS output logic signals to be latched at their predetermined logic level states during the absence of said clock pulses applied to the logic circuit.

9. The logic circuit of claim 8 wherein said circuit means includes:

a translation circuit responsive to said differential ECL logic output signals and said clock pulse for providing first and second differential currents at first and second outputs thereof; and

a latch circuit coupled to said first and second outputs of said translation circuit and receiving said clock pulse for providing said CMOS control signals and latching the same to their predetermined levels during the duration of said clock pulse.

10. The logic circuit of claim 9 wherein said output circuit means includes:

a first output buffer stage having first and second inputs and an output, said first input being coupled to said first output of said circuit means, said second input being coupled to a first output of said feedback circuit means at which is provided said first control signal and said output being coupled to said first output of the logic circuit; and

a second output buffer stage having first and second inputs and an output, said first input being coupled to said second output of said circuit means, said second input being coupled to a second output of said feedback circuit means at which is provided said second control signal and said output being coupled to said second output of the logic circuit.

11. The logic circuit of claim 10 wherein said inverter circuit means includes:

a first inverter having an input and an output, said input being coupled to said second output of said circuit means and said output being said first output of said inverter circuit means; and

a second inverter having an input and an output, said input being coupled to said first output of said circuit means and said output being said second output of said inverter circuit means.

12. An integrated memory circuit including an ECL input logic signal to CMOS output logic translation and latch circuit wherein said translation and latch circuit comprises:

input buffer means responsive to ECL input logic signals for providing differential ECL logic output signals;

circuit means responsive both to applied clock pulses and said differential ECL logic output signals for providing first and second CMOS control signals at first and second outputs thereof and for latching said CMOS control signals to a predetermined logic level during the absence of said applied clock pulses;

inverter circuit means responsive to said first and second CMOS control signals for providing first and second complementary control signals; and

output circuit means responsive to said first and second CMOS control signals and said first and second control signals for providing first and second complementary CMOS output logic signals at first and second outputs of the translation and latch circuit, said inverter circuit means causing said CMOS output logic signals to be latched at their predetermined logic level states between said applied pulses.

13. The memory circuit of claim 12 wherein said circuit means includes:

a translation circuit responsive to said differential ECL logic output signals and said clock pulse for providing first and second differential currents at first and second outputs thereof; and

a latch circuit coupled to said first and second outputs of said translation circuit and receiving said clock pulse for providing said CMOS control signals and latching the same to their predetermined levels during the duration of said clock pulse.

14. The memory circuit of claim 13 wherein said output circuit means includes:

a first output buffer stage having first and second inputs and an output, said first input being coupled to said first output of said circuit means, said second input being coupled to a first output of said inverter circuit means at which is provided said first control signal and said output being coupled to said first output of the translation and latch circuit; and

a second output buffer stage having first and second inputs and an output, said first input being coupled to said second output of said circuit means, said second input being coupled to a second output of said inverter circuit means at which is provided said second control signal and said output being coupled to said second output of the translation and latch circuit.

15. The memory circuit of claim 14 wherein said inverter circuit means includes:

a first inverter having an input and an output, said input being coupled to said second output of said circuit means and said output being said first output of said inverter circuit means; and

a second inverter having an input and an output, said input being coupled to said first output of said circuit means and said output being said second output of said inverter circuit means.