Digital computer having an interconnect mechanism stacked above a semiconductor substrate
First Claim
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1. A digital device having an interconnect matrix stacked above a semiconductor substrate comprised of:
- a plurality of storage means intergrated into a surface of said substrate for storing operands and control signals;
an insulating layer over said storage means and said surface;
said storage means having inputs and outputs penetrating through said insulating layer; and
a nonmagnetic interconnect matrix on said insulating layer including a plurality of spaced-apart input buses and output buses on said insulating layer coupled respectively to said inputs and outputs of said storage means;
said interconnect matrix further including a plurality of nonmagnetic three-terminal logic gates on said insulating layer for receiving said operands from said input buses on a first one of said terminals, receiving said control signals on a second one of said terminals, and selectively passing said received operands through a third of said terminals, to said output buses in response to said control signals.
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Abstract
In the disclosed computer, a plurality of register means for storing digital operands and control signals are in a semiconductor substrate; an arithmetic means for performing functional opertions on the operands are also in the substrate; an insulating layer covers the register means and the arithmetic means; and an interconnect matrix is on top of this insulating layer. The interconnect matrix includes pluralities of logic gates coupled through the insulating layer to the register means and arithmetic means and selectively interconnects them in response to the control signals.
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Citations
10 Claims
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1. A digital device having an interconnect matrix stacked above a semiconductor substrate comprised of:
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a plurality of storage means intergrated into a surface of said substrate for storing operands and control signals; an insulating layer over said storage means and said surface; said storage means having inputs and outputs penetrating through said insulating layer; and a nonmagnetic interconnect matrix on said insulating layer including a plurality of spaced-apart input buses and output buses on said insulating layer coupled respectively to said inputs and outputs of said storage means; said interconnect matrix further including a plurality of nonmagnetic three-terminal logic gates on said insulating layer for receiving said operands from said input buses on a first one of said terminals, receiving said control signals on a second one of said terminals, and selectively passing said received operands through a third of said terminals, to said output buses in response to said control signals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification