Digital computer having an interconnect mechanism stacked above a semiconductor substrate

• US 5,148,256 A
• Filed: 02/23/1981
• Issued: 09/15/1992
• Est. Priority Date: 02/23/1981
• Status: Expired due to Fees

• Current Assignee: Burroughs Incorporated (Terreno Realty Corp.)
• Original Assignee: Unisys Corporation
• Inventors: Roesner, Bruce B., Potash, Hanan, Genter, Melvyn E.
• Primary Examiner(s): Larkins, William D.
• Application Number:
  US07/237,429
• Time in Patent Office: 4,222 Days
• Field of Search: 340/825.89, 340/825.94, 340/45, 340/59, 340/15, 340/2
• US Class Current: 257/50
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: Y10S 257/91 Diode arrays, e.g. diode read-only memory array

Abstract

In the disclosed computer, a plurality of register means for storing digital operands and control signals are in a semiconductor substrate; an arithmetic means for performing functional opertions on the operands are also in the substrate; an insulating layer covers the register means and the arithmetic means; and an interconnect matrix is on top of this insulating layer. The interconnect matrix includes pluralities of logic gates coupled through the insulating layer to the register means and arithmetic means and selectively interconnects them in response to the control signals.

Claims

1. A digital device having an interconnect matrix stacked above a semiconductor substrate comprised of:

a plurality of storage means intergrated into a surface of said substrate for storing operands and control signals;

an insulating layer over said storage means and said surface;

said storage means having inputs and outputs penetrating through said insulating layer; and

a nonmagnetic interconnect matrix on said insulating layer including a plurality of spaced-apart input buses and output buses on said insulating layer coupled respectively to said inputs and outputs of said storage means;

said interconnect matrix further including a plurality of nonmagnetic three-terminal logic gates on said insulating layer for receiving said operands from said input buses on a first one of said terminals, receiving said control signals on a second one of said terminals, and selectively passing said received operands through a third of said terminals, to said output buses in response to said control signals.

2. A digital device according to claim 1 wherein each gate of said plurality includes a mask selectable diode on said insulating layer coupling one of said input buses to one of said output buses.

3. A digital device according to claim 1 wherein each gate of said plurality includes a resistive means on said insulating layer that irreversibly switches from a relatively high resistance state to a relatively low resistance state upon the application of a threshold voltage thereacross coupling one of said input buses to one of said output buses.

4. A digital device according to claim 1 wherein said logic gates in said interconnect matrix on said insulating layer are AND-OR logic gates.

5. A digital device according to claim 1 wherein each of said logic gates consists essentially of only three diodes on said insulating layer.

6. A digital device according to claim 1 wherein each logic gate in said plurality is formed by one metal line, a plurality of spaced-apart semiconductor lines crossing said one metal line, and three conductive paths between three of said semiconductor lines and said one metal line.

7. A digital device according to claim 6 wherein said conductive paths are mask selectable.

8. A digital device according to claim 7 wherein each mask selectable path includes a Schottky diode.

9. A digital device according to claim 6 wherein said conductive paths are electrically selectable.

10. A digital device according to claim 9 wherein each electrically selectable path includes a resistive means that irreversibly switches from a relatively high resistance state to a relatively low resistance state upon the application of a threshold voltage thereacross.