Semiconductor chip assemblies having interposer and flexible lead

• US 5,148,266 A
• Filed: 09/24/1990
• Issued: 09/15/1992
• Est. Priority Date: 09/24/1990
• Status: Expired due to Term

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Ist Associates, Inc.
• Inventors: Khandros, Igor Y., DiStefano, Thomas H.
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): CLARK, SHEILA V
• Application Number:
  US07/586,758
• Time in Patent Office: 722 Days
• Field of Search: 357/80, 357/72, 357/74, 357/68, 357/75
• US Class Current: 257/773
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/822 the substrate being a semiconductor, using silicon technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/274 by blanket deposition of the material of the layer connector
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/0652 Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06579 TAB carriers; beam leads
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/3164 the coating being a foil
• CPC Class Codes: H01L 23/49805 the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/4985 Flexible insulating substrates H01L23/49572 and H01L23/49855 take precedence
• CPC Class Codes: H01L 23/49861 Lead-frames fixed on or encapsulated in insulating substrates H01L23/4985, H01L23/49805 take precedence
• CPC Class Codes: H01L 24/27 : Manufacturing methods
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H05K 2201/10378 : Interposers
• CPC Class Codes: Y10T 29/4913 : Assembling to base an electrical component, e.g., capacitor, etc.

Abstract

A semiconductor chip assembly is mounted to contact pads in a compact area array. An interposer is disposed between the chip and the substrate. The contacts on the chip are connected to terminals on the interposer by flexible leads extending through apertures in the interposer. The terminals on the interposer in turn are bonded to the contact pads on the substrate. Flexibility of the leads permits relative movement of the contacts on the chip relative to the terminals and the contact pads of the substrate and hence relieves the stresses caused by differential thermal expansion. The arrangement provides a compact structure similar to that achieved through flip-chip bonding, but with markedly increased resistance to thermal cycling damage.

Claims

1. A semiconductor chip assembly comprising:

(a) a semiconductor chip having a front surface and a plurality of contacts disposed in a pattern on said front surface, said pattern encompassing a contact pattern area on said front surface;

(b) a sheetlike dielectric interposer overlying said front surface of said chip, said interposer having a first surface facing toward said chip and a second surface facing away from said chip, an area of said interposer overlying said contact pattern area of said chip, said interposer having apertures extending from said first surface to said second surface;

(c) a plurality of terminals disposed in a pattern on said second surface of said interposer, at least some of said terminals being disposed in said area of said interposer overlying said contact pattern area, each such terminal being associated with one of said contacts on said chip; and

(d) a flexible conductive lead extending between each said terminal and the associated one of said contacts, each such lead extending through one of said apertures, each said lead having a contact end connected to the associated contact and a terminal end connected to the associated terminal, said terminals being moveable relative to the contact ends of said leads so as to compensate for thermal expansion of said chip.

2. A chip assembly as claimed in claim 1 wherein said interposer is flexible.

3. A chip assembly as claimed in claim 1 wherein each said terminal is generally planar and overlies said second surface of said interposer.

4. A chip assembly as claimed in claim 3 wherein each said terminal is metallic and each said lead includes a metallic wire bonded to the associated terminal and contact.

5. A chip assembly as claimed in claim 3 wherein each said terminal is metallic and each said lead includes a metallic strip formed integrally with the associated terminal and bonded to the associated contact.

6. A chip assembly as claimed in claim 1 wherein each said terminal is disposed adjacent one of said apertures in said interposer, and each said lead extends from one said terminal, through the adjacent aperture to one of said contacts on said chip.

7. A chip assembly as claimed in claim 6 wherein each said aperture in said interposer is aligned with one of said contacts on said chip and each said lead is connected to one of said contacts on said chip at a junction disposed in one of said apertures.

8. A chip assembly as claimed in claim 1 wherein each said lead has a curved portion.

9. A chip assembly as claimed in claim 8 wherein each said curved portion is curved in a direction parallel to said second surface of said interposer.

10. A chip assembly as claimed in claim 8 wherein each said curved portion is curved in a direction perpendicular to said second surface of said interposer.

11. A chip assembly as claimed in claim 1 further comprising a compliant dielectric encapsulant filling said apertures and surrounding said leads.

12. A chip assembly as claimed in claim 11 wherein said encapsulant is an elastomer.

13. A chip assembly as claimed in claim 1 further comprising a layer of a compliant dielectric encapsulant overlying said second surface of said interposer and surrounding said leads, said layer of encapsulant having holes aligned with said terminals.

14. A chip assembly as claimed in claim 1 further comprising a layer of a compliant dielectric encapsulant overlying said second surface of said interposer and surrounding said leads, said layer of encapsulant having holes aligned with said terminals, said means for bonding said terminals to said pads on said substrate including masses of electrically conductive bonding material disposed in said holes in said layer of encapsulant.

15. A chip assembly as claimed in claim 1 further comprising an adhesive disposed between said first surface of said interposer and said front surface of said chip.

16. A chip assembly as claimed in claim 1 wherein said terminals are substantially evenly spaced throughout area of said interposer overlying said contact pattern area.

17. A chip assembly as claimed in claim 16 wherein said terminals are disposed in a rectilinear grid pattern.

18. A chip assembly as claimed in claim 1 wherein said contacts are substantially evenly spaced throughout said contact pattern area.

19. A chip assembly as claimed in claim 1 wherein said contacts on said chip are disposed in a peripheral region of said chip adjacent the edge of said array area, said array area having a central region devoid of said contacts, at least some of said leads extending inwardly from contacts in said peripheral region to terminals overlying said central region.

25. A chip assembly as claimed in claim 2 wherein said interposer is compliant so that each said terminal is displaceable towards said chip, whereby said terminals can be displaced towards the chip upon engagement of the assembly with test probes to thereby compensate for non-uniformities in dimensions and facilitate engagement of test probes with said terminals.

20. A semiconductor chip assembly comprising:

(a) A semiconductor chip having a front surface and a plurality of contacts disposed in a pattern on said front surface, said pattern encompassing a contact pattern area on said front surface;

(b) a sheetlike dielectric interposer overlying said front surface of said chip, said interposer having a first surface facing toward said chip and a second surface facing away from said chip, an area of said interposer overlying said contact pattern area of said chip, said interposer having apertures extending from said first surface to said second surface;

(c) a plurality of terminals disposed in a pattern on said second surface of said interposer, at least some of said terminals being disposed in said area of said interposer overlying said contact pattern area, each such terminal being associated with one of said contacts on said chip;

(d) a flexible conductive lead extending between each said terminal and the associated one of said contacts, each such lead extending through one of said apertures, each said lead having a contact end connected to the associated contact and a terminal and connected to the associated terminal; and

(e) a substrate having a top surface facing toward said second surface of said interposer and a plurality of contact pads disposed on said top surface in a pattern corresponding to said pattern of terminals so that said pads confront said terminals and means for bonding said pads on said substrate to said terminals on said interposer, said terminals being moveable relative to the contact ends of said leads so that movement of said terminals relative to the contact ends of said leads can compensate for movement of said contacts on said chip relative to said contact pads on said substrate arising from thermal expansion.

21. A chip assembly as claimed in claim 20 wherein said means for connecting said terminals to said pads of said substrate includes a mass of electrically conductive bonding material disposed between each said terminal and the associated contact pad of said substrate.

22. A chip assembly as claimed in claim 20 wherein said bonding material includes a polymeric material.

23. A chip assembly as claimed in claim 20 wherein said bonding material includes solder.

24. A chip assembly as claimed in claim 20 wherein said interposer is flexible.