Logic circuit and data processing apparatus using the same

• US 5,148,387 A
• Filed: 02/15/1990
• Issued: 09/15/1992
• Est. Priority Date: 02/22/1989
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Yano, Kazuo, Nakagawa, Tetsuya, Ishibashi, Koichiro, Shimohigashi, Katsuhiro, Minato, Osamu
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US07/480,674
• Time in Patent Office: 943 Days
• Field of Search: 364/784-786, 307/464
• US Class Current: 708/702
• CPC Class Codes: G06F 7/5016 forming at least one of the output signals directly from the minterms of the input signals, i.e. with a minimum number of gate levels

Abstract

A logic circuit includes first, second, third, fourth, fifth and sixth field effect transistors or FETs, input nodes and an output node. The fifth and sixth FETs are connected to the output node. The first and third FETs are connected to the fifth FET. The second and fourth FETs are connected to the sixth FET. The first and second FETs are connected to the first input node. The third and fourth FETs are connected to the second node. A first signal is supplied to the first input node. A second signal is supplied to gate electrodes of the first and fourth FETs. A signal having a phase opposite to the second signal is supplied to gate electrodes of the second and third FETs. A third signal is supplied to the second input node. One signal selected from the first, second and the third signals is supplied to the gate electrode of the fifth FET. A signal having a phase opposite to the signal supplied to the gate electrode of the fifth FET is supplied to the gate electrode of the sixth FET. An output signal related to the first, second and third input signals is generated from the output node. The output signal is, for example, a carry output signal or alternatively a majority decision logic output signal.

Claims

1. A logic circuit, comprising:

(1) first to sixth switching elements, each of which includes a first electrode, a second electrode and a control input electrode and in each of which electrical conduction and non-conduction between said first electrode and said second electrode are controlled in dependence on the signal levels supplied to said control input electrode; and

(2) first to fifth nodes;

wherein a current path between said first electrode and said second electrode of said first switching element is connected between said first node and said third node,

wherein a current path between said first electrode and said second electrode of said second switching element is connected between said first node and said fourth node,

wherein a current path between said first electrode and said second electrode of said third switching element is connected between said second node and said third node,

wherein a current path between said first electrode and said second electrode of said fourth switching element is connected between said second node and said fourth node,

wherein a current path between said first electrode and said second electrode of said fifth switching element is connected between said third node and said fifth node,

wherein a current path between said first electrode and said second electrode of said sixth switching element is connected between said fourth node and said fifth node,

wherein a first input signal is supplied to said first node,

wherein a second input signal is supplied to said control input electrode of said first switching element and to said control input electrode of said fourth switching element,

wherein a signal having a phase opposite to that of said second input signal is supplied to said control input electrode of said second switching element and to said control input electrode of said third switching element,

wherein a third input signal is supplied to said second node,

wherein one signal selected from said first, second and third input signals is supplied to said control input electrode of said fifth switching element,

wherein a signal having a phase opposite to that of said signal supplied to said control input electrode of said fifth switching element is supplied to said control input electrode of said sixth switching element; and

wherein a signal related to said first, second and third input signals is generated from said fifth node.

2. A logic circuit according to claim 1,

wherein said first to sixth switching elements are constituted by field effect transistors, respectively.

3. A data processing apparatus including a full adder, wherein said full adder includes a carry signal generating circuitry constituted by the logic circuit as set forth in claim 1.

4. A data processing apparatus according to claim 3,

wherein said first to sixth switching elements are constituted by field effect transistors, respectively.

5. A logic circuit, comprising:

(1) first to sixth switching elements, each of which includes a first electrode, a second electrode and a control input electrode and in each of which electrical conduction and non-conduction between said first electrode and said second electrode are controlled in dependence on the signal levels supplied to said control input electrode; and

(2) first to fifth nodes;

wherein a current path between said first electrode and said second electrode of said first switching element is connected between said first node and said third node.

wherein a current path between said first electrode and said second electrode of said second switching element is connected between said first node and said fourth node.

wherein a current path between said first electrode and said second electrode of said third switching element is connected between said second node and said third node,

wherein a current path between said first electrode and said second electrode of said fourth switching element is connected between said second node and said fourth node,

wherein a current path between said first electrode and said second electrode of said fifth switching element is connected between said third node and said fifth node,

wherein a current path between said first electrode and said second electrode of said sixth switching element is connected between said fourth node and said fifth node.

wherein a first input signal is supplied to said first node,

wherein a second input signal is supplied to said control input electrode of said first switching element and to said control input electrode of said fourth switching element,

wherein a signal having a phase opposite to that of said second input signal is supplied to said control input electrode of said second switching element and to said control input electrode of said third switching element,

wherein a third input signal is supplied to said second node,

wherein one signal selected from said first, second and third input signals is supplied to said control input electrode of said fifth switching element,

wherein a signal having a phase opposite to that of said signal supplied to said control input electrode of said fifth switching element is supplied to said control input electrode of said sixth switching element,

wherein a signal related to said first, second and third input signals is generated from said fifth node, and

wherein said generated signal is a carry output signal related to said first, second and third input signals.

6. A logic circuit according to claim 5,

wherein said first to sixth switching elements are constituted by field effect transistors, respectively.

7. A logic circuit, comprising:

(1) first to sixth switching elements, each of which includes a first electrode, a second electrode and a control input electrode and in each of which electrical conduction and non-conduction between said first electrode and said second electrode are controlled in dependence on the signal levels supplied to said control input electrode; and

(2) first to fifth nodes;

wherein a current path between said first electrode and said second electrode of said first switching element is connected between said first node and said third node,

wherein a current path between said first electrode and said second electrode of said second switching element is connected between said first node and said fourth node,

wherein a current path between said first electrode and said second electrode of said third switching element is connected between said second node and said third node,

wherein a current path between said first electrode and said second electrode of said fourth switching element is connected between said second node and said fourth node,

wherein a current path between said first electrode and said second electrode of said fifth switching element is connected between said third node and said fifth node,

wherein a current path between said first electrode and said second electrode of said sixth switching element is connected between said fourth node and said fifth node,

wherein a first input signal is supplied to said first node,

wherein a second input signal is supplied to said control input electrode of said first switching element and to said control input electrode of said fourth switching element,

wherein a signal having a phase opposite to that of said second input signal is supplied to said control input electrode of said second switching element and to said control input electrode of said third switching element,

wherein a third input signal is supplied to said second node,

wherein one signal selected from said first, second and third input signals is supplied to said control input electrode of said fifth switching element,

wherein a signal having a phase opposite to that of said signal supplied to said control input electrode of said fifth switching element is supplied to said control input electrode of said sixth switching element,

wherein a signal related to said first, second and third input signals is generated from said fifth node, and

wherein said generated signal is a majority decision output signal related to said first, second and third input signals.

8. A logic circuit according to claim 7,

wherein said first to sixth switching elements are constituted by field effect transistors, respectively.