MOS dynamic semiconductor memory cell

• US 5,148,393 A
• Filed: 07/06/1989
• Issued: 09/15/1992
• Est. Priority Date: 07/07/1988
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Furuyama, Tohru
• Primary Examiner(s): Bowler, Alyssa H.
• Application Number:
  US07/375,909
• Time in Patent Office: 1,167 Days
• Field of Search: 365/189.09, 365/181, 365/190, 365/226, 307/296.1, 307/296.2
• US Class Current: 365/149
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Abstract

A semiconductor memory according to the present invention comprises a MOS dynamic semiconductor memory cell in which one terminal of a current path of one MOS transistor is connected to one capacitor element, the other terminal of the current path of the MOS transistor is connected to a bit line, and a gate electrode of the transistor is connected to a word line, wherein a substrate of the MOS transistor is not connected to a fixed potential terminal, and the potential of the substrate is switched and controlled so that the MOS transistor time-selectively becomes an enhancement type or a depletion type which can prevent a threshold voltage loss over time.

Claims

1. A semiconductor memory comprising:

a bit line and a word line;

a substrate potential line;

a memory cell including a capacitor element, and a MOS transistor having a drain, a source, a gate, and a back gate, one of said drain and said source being connected to said capacitor element, the other of said drain and said source being connected to said bit line, said gate being connected to said word line, and said back gate being connected to said substrate potential line; and

a potential switching device, connected to said substrate potential line, for selectively switching a potential of said back gate of said MOS transistor.

2. A memory according to claim 1, wherein said potential switching device controls the potential of said back gate of said MOS transistor at every predetermined period of time so that said MOS transistor becomes an enhancement type or a depletion type which can prevent a threshold voltage loss.

3. A memory according to claim 1, wherein said MOS transistor comprises first and second impurity layers of a first conductivity type formed in a surface of a well region of a second conductivity type which is formed in a semicodncutor substrate of the first conductivity type, a gate insulating film formed on said well region and underlying said gate, and said capacitor element comprises a third impurity layer of the first conductivity type for electric charge storage, formed in said well region so as to be in contact with one of said first impurity layer and second impurity layer of said MOS transistor, a capacitor electrode located above said third impurity layer, and a capacitor insulating film interposed between said capacitor electrode and said third impurity layer.

4. A memory according to claim 1, wherein said MOS transistor comprises first and second impurity layers of a first conductivity type formed in a semiconductor region of a second conductivity type, said semiconductor region being formed in an insulating layer formed on an insulating substrate, and a gate insulating film formed on said semiconductor region, said gate being formed on said gate insulating film;

and wherein said capacitor element comprises a capacitor insulating film formed on a portion of one of said first and second impurity layer, and a capacitor electrode formed on said capacitor insulating film, wherein said portion of one of said first and second impurity layers is used for storing an electric charge.

5. A memory according to claim 1, wherein said potential switching device is controlled by timing pulses for selecting said word line.

6. A memory according to claim 2 wherein said potential switching device is controlled by timing pulses for selecting said word line.

7. A memory according to claim 3, wherein said potential switching device is controlled by timing pulses for selecting said word line.

8. A memory according to claim 4, wherein said potential switching device is controlled by timing pulses for selecting said word line.

9. A memory according to claim 1, wherein said MOS transistor comprises first and second impurity layers of a first conductivity type formed in a semiconductor region of a second conductivity type, said semiconductor region being formed in an insulating layer formed on an insulating substrate, and a gate insulating film formed on said semiconductor region, said gate being formed on said gate insulating film;

and wherein said capacitor element comprises a capacitor insulating film formed on a portion of one of said first and second impurity layers, and a capacitor electrode formed on said capacitor insulating film, wherein said portion of one of said first and second impurity layers is used for storing an electric charge, and a third impurity layer of the first conductivity type is formed in a surface of said insulating substrate in a position corresponding to said semiconductor region.

10. A semiconductor memory comprising:

a bit line and a word line;

a substrate potential line;

a memory cell including a capacitor element, and a MOS transistor having a drain, a source, a gate, and a back gate, one of said drain and said source being connected to said capacitor element, the other of said drain and said source being connected to said bit line, said gate being connected to said word line, and said back gate being connected to said substrate potential line; and

a potential switching device, connected to said substrate potential line, for selectively switching a potential of said back gate of said MOS transistor at predetermined periods of time so that said MOS transistors becomes one of an enhancement type and a depletion type which can prevent threshold voltage loss.

11. A semiconductor memory comprising:

a bit line and a word line;

a substrate potential line;

a memory cell including a capacitor element, and a MOS transistor having a drain, a source, a gate, and a back gate, one of said drain and said source being connected to said capacitor element, the other of said drain and said source being connected to said bit line, said gate being connected to said word line, and said back gate being connected to said substrate potential line; and

a potential switching device, connected to said substrate potential line, for selectively switching a potential of said back gate of said MOS transistor at predetermined periods of time so that said MOS transistor becomes one of an enhancement type and a depletion type which can prevent threshold voltage loss, said potential switching device being controlled by timing pulses for selecting said word line.