Neural network integrated circuit device having self-organizing function

• US 5,148,514 A
• Filed: 04/24/1990
• Issued: 09/15/1992
• Est. Priority Date: 05/15/1989
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Arima, Yutaka, Hanibuchi, Toshiaki, Tomioka, Ichiro
• Primary Examiner(s): MacDonald, Allen R.
• Assistant Examiner(s): DAVIS, GEORGE B
• Application Number:
  US07/515,476
• Time in Patent Office: 875 Days
• Field of Search: 364/513, 364/807, 307/201, 307/353, 395/24
• US Class Current: 706/34
• CPC Class Codes: G06N 3/063 using electronic means

Abstract

An extension directed integrated circuit device having a learning function on a Boltzmann model, includes a plurality of synapse representing units arrayed in a matrix to form a rectangle including a first and second triangles on a semiconductor chip, a plurality of neuron representing units and a plurality of educator signal control circuits which are arranged along first and second sides of the rectangle, and a plurality of buffer circuits arranged along third and fourth sides of the rectangle. The first side is opposite to the third side, and the second side is opposite to the fourth side. Axon signal transfer lines and dendrite signal lines are so arranged that the neuron representing units are full-connected in each of the first right triangle the second right triangle. Alternatively, axon signal lines and dendrite signal ines are arranged in parallel with rows and columns of the synapse representing unit matrix, so that the neuron representing units are full-connected in the rectangle. Each synapse representing unit is connected to a pair of axon signal transfer lines and a pair of dendrite signal transfer lines.

Claims

1. An integrated circuit device having a learning function, being modelled on nerve cells, comprising:

a plurality of nerve cell representing units simulating functions of nerve cell bodies;

a plurality of axon representing signal lines each receiving a signal indicating a state of an associated nerve cell representing unit;

a plurality of dendrite representing signal lines provided in correspondence to respective ones of said plurality of nerve cell representing units for transferring signals to corresponding nerve cell representing units; and

a plurality of synapse representing units provided on respective ones of crosspoints between said plurality of axon representing signal lines and said plurality of dendrite representing signal lines for coupling related axon representing signal lines with related dendrite representing signal lines with specific synapse representing loads, said specific synapse representing loads of respective synapse representing units being set at optimum values in learning of said integrated circuit device,

said plurality of synapse representing units being arrayed to be at lest substantially in the form of a first right triangle, said right triangle having first and second sides other than its hypotenuse,

said plurality of nerve cell representing units being arranged in the form of a column along said first side of said first right triangle.

2. An integrated circuit device in accordance with claim 1, wherein

said integrated circuit device is integrated on one semiconductor chip.

3. An integrated circuit device in accordance with claim 1, further comprising a plurality of axon representing driving units provided in correspondence to respective ones of said plurality of axon representing signal lines for transferring state signals onto corresponding said axon representing signal lines,

said plurality of axon representing driving units being arranged along said second side of said first right triangle.

4. An integrated circuit device in accordance with claim 3, further comprising a plurality of second synapse representing units being arrayed symmetrically to said plurality of synapse representing units with respect to said hypotenuse of said first right triangle, whereby said integrated circuit device comprises substantially rectangularly arrayed synapse representing units having common structures, and

a second right triangle formed by said plurality of second synapse representing units has third and fourth sides being opposite to said first and second sides of said first right triangle respectively,

said integrated circuit device further comprising second nerve cell representing units for said second synapse representing units, said second nerve cell representing units being arranged along said fourth side.

5. An integrated circuit device in accordance with claim 4, further comprising a plurality of axon driving units being arranged along said third side for transferring state signals to said second synapse representing units.

6. An integrated circuit device in accordance with claim 4, further comprising a plurality of second axon representing driving units being arranged along said fourth side in correspondence to respective ones of said second nerve cell representing units for transferring state signals of corresponding said nerve cell representing units onto related said axon representing signal lines,

a signal transfer direction of said second axon representing driving units being opposite to a direction for transferring dendrite representing signals onto related said nerve cell units.

7. An integrated circuit device in accordance with claim 4, further comprising a plurality of educator signal control units provided for respective ones of said plurality of nerve cell representing units with respect to said first right triangle and said second nerve cell representing units with respect to said second right triangle for setting states of corresponding nerve cell representing units in accordance with educator information to be learned in said learning of said integrated circuit device,

said educator signal control units for said plurality of nerve cell representing units with respect to said first right triangle are arranged along said first side of said first right triangle, and

said educator signal control units for said second nerve cell representing units are arranged along said fourth side of said second right triangle.

8. An integrated circuit device in accordance with claim 1, further comprising a plurality of axon representing driving units provided in correspondence to respective ones of said plurality of nerve cell representing units for transferring state signals of corresponding nerve cell representing units onto corresponding axon representing signal lines,

said plurality of axon representing driving units being arranged along said first side of said first right triangle so that a signal transfer direction on said dendrite representing signal lines related to corresponding said nerve cell representing units is opposite to a signal transfer direction on related said axon representing signal lines.

9. An integrated circuit device in accordance with claim 1, further comprising a plurality of educator signal control units provided in correspondence to respective ones of said nerve cell representing units for setting states of corresponding said nerve cell representing units in accordance with educator information to be learned in said learning of said integrated circuit device,

said educator signal control units being arranged along said first side of said first right triangle.

10. An integrated circuit device in accordance with claim 1, further comprising a plurality of educator signal control units provided in correspondence to respective ones of said representing signal lines for transferring educator information to be learned to related said axon representing signal lines in said learning of said integrated circuit device,

said educator signal control units being arranged along said second side of said first right triangle.

11. An integrated circuit device in accordance with claim 1, wherein

each synapse representing unit includes means coupled to a different pair of axon representing signal lines and a different pair of said dendrite representing signal lines for weighting received pair of said axon representing signals with the same synapse representing load and transferring weighted axon representing signals to respective ones of said different pair of dendrite representing signal lines respectively,

whereby one synapse representing unit represents symmetrical synapse representing loads and couples a pair of nerve cell representing units to another pair of nerve cell representing units.

12. An integrated circuit device in accordance with claim 1, wherein

said axon representing signal lines and said dendrite representing signal lines are so arranged that one synapse representing unit couples a different pair of nerve cell representing units to another different pair of nerve cell representing units and said nerve cell representing units are interconnected to form a full connection neural network.

13. An integrated circuit device in accordance with claim 1, wherein

each synapse representing unit includes:

learning control circuit means being activated in said learning for receiving a first axon representing signal Si and a second axon representing signal Sj and deriving change value information of synapse representing load of a corresponding synapse representing unit in accordance with predetermined learning rules,

synapse representing load circuit means for changing a value of said synapse representing load in accordance with said change value information from said learning control circuit means and holding said changed synapse representing load Wij,

first synapse representing coupling operating circuit means for transferring a first product signal indicating the product Wij·

Si of said synapse representing load Wij and said first axon representing signal Si to a first dendrite representing signal line in response to said synapse representing load Wij being held in said synapse representing load circuit means and said first axon representing signal Si,

second synapse representing coupling operating circuit means for transferring a second product signal indicating the product Wij·

Sj of said synapse representing load Wij and said second axon representing signal Sj to a second dendrite representing signal line in response to said synapse representing load Wij being held in said synapse representing load circuit means and said second axon representing signal Sj,

said synapse representing unit representing both of symmetrical synapse representing loads Wij and Wji, where Wij=Wji.

14. An integrated circuit device in accordance with claim 13, wherein

said learning has a plus phase in which respective states of both input nerve cell representing units included in an input layer for receiving input data from the exterior and output nerve cell representing units included in an output layer for deriving output data indicating results of processing to the exterior are clamped at educator information to be learned in a neural network formed through one or more said integrated circuit devices and a minus phase in which only states of said input nerve cell representing units are clamped at said educator information to be learned, and

each learning control circuit comprises:

means for operating the product of said first axon representing signal Si and said second axon representing signal Sj, said first and second axon representing signals being binary digital values,

first and second storage means for storing the output of said product operating means, said first storage means storing the result S⁺ i·

S⁺ j of product operation in said plus phase, said second storage means storing the result S^- i·

S^- j of product operation in said minus phase, said first and second storage means storing the results of product operation in corresponding learning phases in response to externally supplied control signals, and

circuit means for outputting a signal indicating an amount Δ

Wij of correction for said synapse representing load Wij in accordance with the following relational expression;

space="preserve" listing-type="equation">Δ

Wij=η

·

(S.sup.+ i·

S.sup.+ j-S.sup.- i·

S.sup.- j)

where η

represents a predetermined learning coefficient, in response to said values stored in said first and second storage means.

15. An integrated circuit device in accordance with claim 13, wherein

said learning has a plus phase mode in which states of both input nerve cell representing units included in an input layer for receiving input data supplied from the exterior and output nerve cell representing units included in an output layer for outputting results of processing are clamped at educator information to be learned and a minus phase mode in which states of said input nerve cell units are clamped at said educator information to be learned in a neural network formed through one or more said integrated circuit devices,

each learning control circuit means comprises:

means for operating the product of said first axon representing signal Si and said second axon representing signal Sj, both of said first and second axon representing signals being binary digital signals,.

first register means coupled to the output of said means for operating the product for holding and outputting a received product operation signal in response to a first control signal,

second register means coupled to the output of said first register means for holding and outputting the output of said first register means in response to a second control signal,

third register means coupled to the output of said second register means for holding and outputting the output of said second register means in response to said first control signal,

means for detecting match/mismatch of the outputs of said first register means and said third register means, and

selective passage means for selectively passing a third control signal in response to the output of said detection means,

said first control signal is generated when said first and second axon representing signals are defined in each mode of said plus phase and said minus phase,

said second control signal is generated when learning modes are switched,

said selective passage means passes said third control signal and supplies same to said synapse representing load circuit means as said synapse representing load change value information when said detection means indicates a mismatch, and

the output of said third register means is supplied to said synapse representing load circuit means as signal information of said synapse representing load change value information,

said plus phase is carried out and then said minus phase is carried out in said learning, whereby said selective passage means outputs a signal indicating the value of a synapse representing load change value Wij being expressed as;

space="preserve" listing-type="equation">Δ

Wij=η

·

(S.sup.+ i·

S.sup.+ j-S.sup.- i·

S.sup.- j)

where S⁺ i and S⁺ j represent said first and second axon representing signals in said plus phase, S^- i and S^- j represent said first and second axon representing signals in said minus phase, and η

represents a predetermined learning coefficient provided by the pulse number of said third control signal.

16. An integrated circuit device in accordance with claim 13, wherein

said learning has a plus phase in which respective states of both input nerve cell representing units included in an input layer for receiving input data from the exterior and output nerve cell representing units included in an output layer for deriving output data indicating results of processing to the exterior are clamped at educator information to be learned in a neural network formed through one or more said integrated circuit devices and a minus phase in which only states of said input nerve cell representing units are clamped at said educator information to be learned,

each of said learning control circuit means comprises:

means for operating the product of said first axon representing signal Si and said second axon representing signal Sj, said first and second axon representing signals being binary digital values,

means for storing the output of said means for operating the product,

circuit means for outputting the following synapse representing load change values;

space="preserve" listing-type="equation">Δ

Wij=η

·

Si·

Sj

through said value stored in said storage means, and

means for setting the sign of said synapse representing load change value in response to a learning mode designating signal supplied from the exterior, said sign setting means setting the sign of said synapse representing load change value positive in said plus phase while setting the sign of said synapse representing load change value negative in said minor phase.

17. An integrated circuit device in accordance with claim 16, wherein

said synapse representing load change value output circuit means includes means for selectively passing a first control signal in response to data stored in said storage means, said first control means being a pulse signal defining said learning coefficient.

18. An integrated circuit device in accordance with claim 13, wherein

said learning control circuit means includes means for outputting said synapse representing load change value information in a pulse train signal and outputting a signal indicating the sign of said synapse representing load change value information, and

each synapse representing load circuit means includes:

counter means, being capable of performing count-up and count-down operations, for counting a pulse number corresponding to a synapse representing load change value generated by said learning control circuit means in response to said sign indicating signal derived from corresponding said learning control circuit means, said counter means being capable of counting a value having a bit number larger than a prescribed bit number required for representing said synapse representing load and being adapted to derive a signal value indicating the value and sign of said synapse representing load,

means for detecting whether or not a count value of said counter means is within a range between predetermined maximum and minimum limit values with respect to said synapse representing load, and

means receiving said signal indicating the value of said synapse representing load from said counter means for holding same at a limit value of a corresponding said synapse representing load and outputting same when said detection means detects a count value being out of said range between maximum and minimum limit values of said synapse representing load while transferring said signal indicating said synapse representing load from said counter means when said detection means detects that the count value of said counter means is within said range.

19. An integrated circuit device in accordance with claim 18, wherein

said counter means has specific upper and lower count limit values, and includes:

means for counting said pulse signal received from said learning control circuit means until it reaches each specific upper or lower count limit value even if said count value exceeds said predetermined maximum or minimum limit value of said synapse representing load, and

means for inhibiting a counting operation being in excess of said specific upper or lower limit value when said count value reaches said specific upper or lower limit value.

20. An integrated circuit device in accordance with claim 13, wherein

said learning control circuit means includes means for outputting said change value information of said synapse representing load in a pulse train signal and outputting a signal indicating the sign of said change value information, and

each of said synapse representing load circuits includes:

count means for receiving said change value information indicating signal as a count-up/count-down indicating signal and counting a pulse number of said pulse train signal, said count means having less significant N bits outputting a synapse representing load value, a most significant bit indicating the sign of said synapse representing load, and at least one redundant bit between said less significant N bits and said most significant bit,

first detection circuit means for detecting match/mismatch between data of said most significant bit and data of said redundant bit,

means provided for said less significant N bits for outputting data of said less significant N bits as synapse representing load value data, said synapse representing load value data output means including means for passing said less significant N-bit data in response to a mismatch detecting signal received from said match/mismatch detection circuit means and outputting said less significant N-bit data preceding first supply of said match detecting signal in response to said match detecting signal regardless of said less significant N-bit data, and

means for receiving said synapse representing load change value sign indicating signal and all output bits of said count means, detecting match/mismatch of received said signals and selectively passing said pulse train signal in accordance with the result of said detection, said selective passage means including means for inhibiting passage of said pulse train signal when said result of said detection indicates a match.

21. An integrated circuit device in accordance with claim 20, wherein

said redundant bit is one bit, and

said selective passage means for said less significant N bits includes second selective passage means provided in correspondence to respective ones of said N bits for selectively passing either corresponding bit data or said redundant bit data in response to the output of said first match/mismatch detection circuit means, said second selective passage means passing said redundant bit data when said first match/mismatch detection circuit means indicates a match.

26. An integrated circuit device in accordance with claim 13, wherein

said learning control circuit means outputs information defining said synapse representing load change value in a pulse train signal,

said synapse representing load circuit means includes:

means for storing synapse representing load values, said synapse representing load value storage means including first capacitor means for storing a synapse representing load value representing excitatory coupling in the form of charges and second capacitor means for storing a synapse representing load value representing inhibitory coupling in the form of charges, and

means for changing said synapse representing load values being stored in said synapse representing load value storage means in response to said pulse train signal received from said learning control circuit means, and

said synapse representing coupling operating means includes means for joining weights corresponding to said synapse representing load stored in said synapse representing load value storage means to said axon representing signals on said corresponding axon representing signal lines and transferring the same onto corresponding said dendrite representing signal lines, said transfer means including means for supplying current signals being proportionate to the products of said axon representing signals and stored said synapse representing load values onto corresponding dendrite representing signal lines.

27. An integrated circuit device in accordance with claim 26, wherein

said synapse representing load value change means includes means for transferring respective pulse signals of said pulse train signal received from said learning control circuit means to said first and second capacitor means by capacitive coupling.

28. An integrated circuit device in accordance with claim 26, wherein

said learning control circuit means includes:

means for operating the product of said fist axon representing signal Si and said second axon representing signal Sj, and

means for selectively supplying said pulse train signal to said synapse representing load value change means in response to the output of said product operating means and an externally supplied learning mode designating signal, said pulse train signal being supplied to change said synapse representing load values stored in said first capacitor means and said second capacitor means, said learning mode designating signal designating either a first learning mode in which both axon representing signals of input and output neuron representing units are fixed at the value of educator data to be learned or a second learning mode in which only axon representing signals of said input neuron representing units are fixed at the value of said educator data, and

said selective application means includes means for generating synapse representing load change control pulses representing;

space="preserve" listing-type="equation">Δ

Wij=η

·

Si·

Sj

in said first learning mode while representing;

space="preserve" listing-type="equation">Δ

Wij=-η

·

Si·

Sj

in said second learning mode, where η

corresponds to a number of pulses of said pulse train signal, and Δ

Wij represents the amount of synapse load change.

29. An integrated circuit device in accordance with claim 28, wherein

said amount Δ

Wij of synapse representing load change generated in said first learning control mode is transferred to said first capacitor means through capacitive coupling, and

said amount Δ

Wij of synapse representing load change generated in said second learning mode is transferred to said second capacitor means through capacitive coupling.

30. An integrated circuit device in accordance with claim 13, wherein

said learning of said integrated circuit device has a plus phase in which axon representing signals indicating states of input neuron representing units for receiving input data from an exterior and output neuron representing units for outputting data indicating results of processing to the exterior are clamped at educator information to be learned and a minus phase in which only axon representing signals of said input neuron representing units are clamped at said educator information to be learned in a neural network formed through at least one said integrated circuit device,

each of said learning control circuit means has a first terminal for outputting a first pulse train signal indicating an amount of synapse representing load change in said plus phase and a second terminal for outputting a second pulse train signal indicating an amount of synapse representing load change in said minus phase,

each said learning control circuit means includes:

first capacitor means for coupling said first output terminal of said learning control circuit means with a first node,

first diode means connected between said first node and a first reference potential forwardly from said first node,

second diode means connected said first node and a second node forwardly from said second node,

second capacitor means connected between said second node and said first reference potential,

third capacitor means capacitively coupling said second terminal of said learning control circuit means with a third node,

third diode means connected between said third node and a fourth node forwardly from said third node,

fourth diode means connected between said third node and a second reference potential forwardly from said second reference potential,

fourth capacitor means connected between said fourth node and said second reference potential,

inverter means for inverting a corresponding axon representing signal and transferring the same to a fifth node,

first current supply means for converting said first reference potential to a current signal and transferring the same to corresponding said dendrite representing signal line in response to the potential of said fifth node, the amount of current supply of said first current supply means being determined by the potential of said second node,

second current supply means for converting said first reference potential to a current signal and transferring the same to said corresponding dendrite representing signal line in response to the signal potential of said fifth node, and

third current supply means for converting said first reference potential to a current signal in response to said corresponding axon representing signal, the amount of current supply of said third current supply means being defined by said second reference potential,

said first and second current supply means being complementarily activated with said third current supply means.

31. An integrated circuit device in accordance with claim 30, wherein

each one of said first and second diode means and said third and fourth diode means is formed by an insulated gate field effect transistor having a gate and a first conduction terminal which are connected in common, a second conduction terminal providing a first electrode of a diode series body and a substrate region providing a second electrode of said diode series body, a common node of said first conduction terminal and said gate being coupled to corresponding capacitive coupling means.

32. An integrated circuit device in accordance with claim 13, wherein

said learning control circuit means defines the amount of change of said synapse representing load by outputting a pulse train signal,

said synapse representing load circuit means includes:

means for storing information indicating said synapse representing load in the form of charges, and

means for changing said synapse representing load value stored in said synapse representing load value storage means in response to a pulse signal received from said learning control circuit, said synapse representing load value change means including charge pump means for changing the amount of charges stored in said synapse load value change means in response to a pulse signal received from said learning control circuit means, and

said synapse representing coupling operating circuit means comprises means for joining a weight corresponding to said synapse representing load value stored in said synapse representing load value storage means to an axon representing signal on a corresponding axon representing signal line and transferring the same onto a corresponding dendrite representing signal line, said transfer means including means for supplying a current being proportionate to the product of a signal potential on said corresponding axon representing signal transfer line and said stored synapse representing load value onto said corresponding dendrite representing signal line.

33. An integrated circuit device in accordance with claim 32, wherein

said learning control circuit means comprises:

first deriving means for deriving a first pulse train signal defining the amount of increase of a synapse representing load value, and

second deriving means for deriving a second pulse train signal defining the amount of decrement of said synapse representing load value,

said synapse representing load storage means comprises first capacitor means being connected between a first node and a first reference potential,

said synapse representing load value change means comprises;

second capacitor means for transferring said first pulse signal train to a second node by capacitive coupling,

first diode means connected between said second node and a second reference potential forwardly from said second node,

second diode means connected between said first node and said second node forwardly from said first node,

third capacitor means for transferring said second pulse signal train to a fourth node by capacitive coupling,

third diode means connected between said first node and said fourth node forwardly from said fourth node, and

fourth diode means connected between said fourth node and said first reference potential forwardly from said first reference potential, and

said transfer means of said coupling operating circuit means includes;

means for inverting a corresponding said axon representing signal,

first current supply means being activated in response to the output of said inversion means for converting said second reference potential to a current signal and transferring the same onto said corresponding axon representing signal line, the degree of current conversion of said first current supply means being defined by the potential of said first node, and

second current supply means being activated in response to said corresponding axon representing signal for converting said second reference potential to a current signal and transferring the same onto said corresponding dendrite representing signal line, the degree of conversion into a current signal of said second current supply means being defined by said first reference potential.

34. An integrated circuit device in accordance with claim 33, wherein

said first pulse train signal defines an amount of synapse load change being expressed as:

space="preserve" listing-type="equation">Δ

Wij=η

·

Si·

Sj

and said second pulse train signal defines an amount of synapse load change being expressed as;

space="preserve" listing-type="equation">Δ

Wij=-η

·

Si·

Sj

where Si and Sj represent said first and second axon representing signals and η

represents a predetermined positive learning coefficient,

said first pulse train signal is generated in a learning cycle of a plus phase, while said second pulse train signal is generated in a learning cycle of a minus phase.

35. An integrated circuit device in accordance with claim 33, wherein

a series body of said first and second diode means or a series body of said third and fourth diode means comprises one insulated gate field effect transistor having a first conduction terminal and a gate being coupled to corresponding capacitor means for transferring a pulse train signal by capacitive coupling, a substrate serving as a cathode of said series body and a second conduction terminal serving as an anode of said series body.

36. An integrated circuit device in accordance with claim 1, wherein

each nerve cell representing units includes:

comparison means providing a function corresponding to the body of each nerve cell representing unit, said comparison means having a first input coupled to a corresponding dendrite representing signal line, and

means coupled to a second input of said comparison means for generating a comparative reference voltage of said comparison means, said comparative reference voltage generating means including means being activated by an externally supplied logical binary voltage for generating a voltage being attenuated/vibrated with a time constant and a cycle predetermined particular to said comparative reference voltage generating means with respect to a reference bias potential determined specific to said comparative reference voltage generating means and transferring the same to said second input of said comparison means.

37. An integrated circuit device in accordance with claim 36, wherein

resistive divider means for dividing a first reference potential and a second reference potential and supplying the result to said second input of said comparison means as said reference bias potential, and

attenuated signal generating means for converting a logical binary signal received from the exterior to a signal being attenuated at a predetermined time constant and superposing the same on the output of said resistive divider means.

38. An integrated circuit device in accordance with claim 1, wherein

said plurality of nerve cell units include visible nerve cell units forming an input layer for receiving input data and an output layer for deriving output data, and hidden nerve cell units,

said integrated circuit device further comprises educator signal control circuit means provided in correspondence to respective ones of said nerve cell representing units for deriving educator signals to be learned by said integrated circuit device in said learning of said integrated circuit device in correspondence to respective nerve cell representing units, and

each of said educator signal control circuit means comprises:

first storage means for holding and outputting externally supplied data defining the attribute of a corresponding nerve cell representing unit in an operation mode for defining the attribute of each said nerve cell representing unit while holding an outputting educator data transferring from the exterior through a same terminal as that receiving said attribute defining data in response to a first control signal in an operation mode for setting said educator signal and in said learning mode of said integrated circuit device,

second storage means coupled to the output of said first storage means for holding and outputting said data defining the attribute of said corresponding nerve cell representing unit in response to a second control signal in said operation mode for defining the attribute of said corresponding nerve cell representing unit, said educator signal setting operation mode and said learning operation mode of said integrated circuit device,

third storage means coupled to the output of said first storage means for holding and outputting said data defining the attribute of said corresponding nerve cell representing unit received from said first storage means in said operation mode for defining the attribute of said corresponding nerve cell representing unit while holding and outputting said educator data received from said first storage means in response to a third control signal in said educator signal setting operation mode and said learning operation mode of said integrated circuit device, and

selection circuit means for selecting one of the output of said third storage means, predetermined first fixed data and data representing the state of said corresponding nerve cell representing unit in response to an educator data validation/invalidation indicating signal generated in said learning mode and said data defining an attribute of said corresponding nerve cell representing unit being held in and outputted from said second storage means and transferring the same onto an axon representing signal line provided in correspondence to each nerve cell representing unit,

said attribute of said corresponding nerve cell representing unit defining data and said educator data being serially transferring to first storage means of an adjacent next-stage educator signal control circuit through said first and third storage means in said attribute defining operation mode and said educator signal setting operation mode.

39. An integrated circuit device in accordance with claim 38, further comprising fourth storage means provided between said third storage means and said selection circuit means for holding the output of said third storage means and transferring the same to said selection circuit means as educator data in response to a learning mode indicating signal.

40. An integrated circuit device in accordance with claim 38, further comprising a plurality of series of said first and third storage means, said plurality of series being provided in parallel with each other and connected to different educator signal input terminals, and further comprising means for selecting one of parallel outputs of said plurality of series and transferring the same to said selection circuit means, only the output of said first storage means provided in one of said plurality of series being coupled to the input of said second storage means.

22. An integrated circuit device in accordance with clam 13, wherein

each one of said first and second synapse representing coupling operating circuit means includes:

first gate voltage selection circuit means for selecting either a first reference voltage or a second reference voltage in response to a signal potential on a corresponding axon representing signal line,

second gate voltage selection circuit means for selecting and outputting either an output voltage from said first gate voltage selection circuit means or said second reference voltage in response to a signal, indicating the value of said synapse representing load, outputted from said synapse representing load circuit means,

third gate voltage selection circuit means for selectively outputting either said second reference voltage or said first reference voltage in response to said signal potential on said corresponding axon representing signal line or said signal indicating the value of said synapse representing load outputted from said synapse representing load circuit means, said third gate voltage selection circuit means selecting said second reference voltage only when said signal potential on said corresponding axon representing signal line indicates that corresponding said nerve cell representing unit is in an excitatory state and said signal, indicating the sign of said synapse representing load, received from said synapse representing load circuit means indicates a negative synapse representing load while selecting and outputting said first reference voltage at all other times,

first current supply means for transferring a current corresponding to said signal indicating the value of said synapse representing load onto a corresponding dendrite representing signal line in response to the output from said second gate voltage selection circuit means, and

second current supply means for supplying a current being responsive to positivity/negativity of said synapse representing load in response to the output of said third gate voltage selection circuit means,

wherein a signal indicating the product of an axon representing signal on said axon representing signal line and a synapse representing load represented by said synapse representing load circuit means being transferred onto said dendrite representing signal line.

23. An integrated circuit device in accordance with claim 22, wherein

said synapse representing load means represents the value of a synapse representing load in N bits while representing the sign of said synapse representing load in one bit,

said second voltage selection circuit means includes:

a plurality of first selective passage means provided in correspondence to respective said N bits for passing the output of said first gate voltage selection circuit means in response to corresponding synapse representing load bit data, and

a plurality of second selective passage means provided in correspondence to respective said N bits for passing said second reference voltage in response to corresponding synapse representing load bit data, said selective passage means complementarily operating with said first selective passage means, outputs of said first and second selective passage means being connected to a common node,

said first current supply means includes a plurality of first current conversion means provided in correspondence to respective said N bits for converting said second reference potential to current signals and transferring the same to related dendrite representing signal lines in response to signal potentials on said common nodes of corresponding said first and second selective passage means, each current suppliability of said plurality of first current conversion means being set in response to corresponding synapse representing load bit positions, and

said second current supply means includes second current conversion means for converting said second reference potential to current signals and transferring the same onto said corresponding dendrite representing signal lines in response to the output of said third gate voltage selection circuit means, said second current conversion means having current suppliability greater than that of said first current conversion means.

24. An integrated circuit device in accordance with claim 23, wherein

said first and second current supply means are formed by insulated gate field effect transistors which are connected in parallel between signal lines for transferring said second reference potential and said corresponding dendrite representing signal lines for receiving outputs of corresponding said gate voltage selection means in gates thereof, current suppliability of each said transistor being set by its conductance.

25. An integrated circuit device in accordance with claim 24, further comprising a plurality of second insulated gate field effect transistors provided between respective said insulated gate field effect transistors and said corresponding dendrite representing signal lines for receiving a third reference potential at gates thereof.

41. An integrated circuit device having a learning function, being modelled on nerve cells, comprising:

a plurality of nerve cell representing units simulating functions of nerve cell bodies;

a plurality of axon representing signal lines for transferring signals indicating states of said nerve cell representing units, respectively, to synapse representing circuits;

a plurality of dendrite representing signal lines provided in correspondence to respective ones of said plurality of nerve cell representing units for transferring signals from said synapse representing circuits to corresponding said nerve cell representing units;

said synapse representing circuits provided on respective ones of crosspoints between said plurality of axon representing signal lines and said plurality of dendrite representing signal lines for coupling corresponding said axon representing signal lines with corresponding said dendrite representing signal lines with specific loads, said specific loads of said synapse representing circuits being set at optimum values in learning of said integrated circuit device, said synapse representing circuits being arrayed to substantially form at least one right triangle; and

a plurality of axon representing driving units provided in correspondence to respective ones of said plurality of axon representing signal lines for transferring signals indicating states of corresponding nerve cell representing units onto corresponding axon representing signal lines, said plurality of axon representing driving units being aligned along one of two sides making a right angle of said right triangle,

said plurality of nerve cell representing units being aligned along the other one of said two sides being at right angle.

42. An integrated circuit device having a learning function, being modelled on nerve cells, comprising:

a plurality of nerve cell representing units simulating functions of nerve cell bodies;

a plurality of axon representing signal lines for transferring signals indicating states of said nerve cell representing units, respectively, to synapse representing circuits;

a plurality of dendrite representing signal lines provided in correspondence to respective ones of said plurality of nerve cell representing units for transferring signals from said synapse representing circuits to corresponding said nerve cell representing units;

said synapse representing circuits provided on respective ones of crosspoints between said plurality of axon representing signal lines and said plurality of dendrite representing signal lines for coupling corresponding said axon representing signal lines with corresponding said dendrite representing signal lines with specific loads, said specific loads of said synapse representing circuits being set at optimum values in learning of said integrated circuit device, said synapse representing circuits being arrayed to substantially form at least one right triangle, said plurality of nerve cell representing units being aligned along a first one of two sides being at right angle of said right triangle; and

a plurality of axon representing driving units provided in correspondence to respective ones of said plurality of axon representing signal lines for transferring axon representing signals of related nerve cell representing units to corresponding axon representing signal lines, said plurality of axon representing driving units being arranged along said first side at said right triangle,

a dendrite representing signal line and an axon representing signal line, related to one nerve cell unit, being arranged in parallel with each other,

a signal transfer direction of each of said plurality of axon representing driving units being opposite to a signal transfer direction on said dendrite representing signal line connected to a related nerve cell representing unit.

43. An integrated circuit device having a learning function, being modelled on a nerve cell, said nerve cell model having a nerve cell representing unit simulating the function of a nerve cell body, an axon representing signal line for transferring a signal representing a state of said nerve cell representing unit to a synapse load representing circuit and a dendrite representing signal line for transferring a signal from said synapse load representing circuit to said nerve cell representing unit, said integrated circuit device having a plurality of nerve cell representing units, and comprising:

a plurality of synapse load representing circuits provided on respective ones of crosspoints between respective ones of a plurality of said axon representing signal lines and respective ones of a plurality of said dendrite representing signal lines for coupling said axon representing signal lines with said dendrite representing signal lines between corresponding said nerve cell representing units with specific loads, said specific load representing circuits being arrayed substantially in the form of a rectangle;

a plurality of first axon representing driving units arranged along first side of said rectangle for transferring signals indicating states of corresponding nerve cell representing units onto corresponding axon representing signal lines;

first nerve cell representing units arranged along a second side, being opposite to said first side, of said rectangle, dendrite representing signals associated with axon representing signals of said first axon representing driving units being transferred to dendrite representing signal lines for said first nerve cell representing units;

second axon representing driving units arranged along a third side of said rectangle for transferring axon representing signals indicating states of corresponding nerve cell representing units onto corresponding axon representing signal lines; and

a plurality of second nerve cell representing units aligned along a fourth side, being opposite to said third side, of said rectangle, for receiving dendrite representing signals associated with respective ones of said axon representing signals transferred by said second axon representing driving units,

said plurality of axon representing signal lines and said plurality of dendrite representing signal lines being arranged in column and row directions respectively.

44. An integrated circuit device in accordance with claim 43, wherein

each of said first and second axon representing driving units transfers an axon representing signal so that signals are transferred in the same direction on an axon representing signal line and a dendrite representing signal line being related to one nerve cell representing unit.

45. An integrated circuit device in accordance with claim 43, wherein

each of said first and second axon representing driving units transfers an axon representing signal so that signals are transferred in opposite directions on a dendrite representing signal line and an axon representing signal line being related to one said nerve cell unit.