Methods for testing and burn-in of integrated circuit chips

• US 5,149,662 A
• Filed: 02/21/1992
• Issued: 09/22/1992
• Est. Priority Date: 03/27/1991
• Status: Expired due to Fees

• Current Assignee: Integrated System Assemblies Corp.
• Original Assignee: Integrated System Assemblies Corp.
• Inventors: Eichelberger, Charles W.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): Picardat, Kevin M.
• Application Number:
  US07/839,920
• Time in Patent Office: 214 Days
• Field of Search: 437/8, 437/51, 437/209, 437/211, 148/DIG. 162, 375/74, 375/80
• US Class Current: 438/15
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: G01R 31/2863 Contacting devices, e.g. sockets, burn-in boards or mounting fixtures in general G01R1/04
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/24195 the item being a discrete passive component
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01018 Argon [Ar]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: Y10T 29/49004 : including measuring or testing of device or component part

Abstract

Packaging methods and configurations are disclosed for placing electronic integrated circuit chips into operable chip systems in a manner to facilitate burn-in and testability thereof. The invention addresses the problem of testing bare integrated circuit chips before they are committed to a multichip module. Further, it addresses the problem of burning-in bare chips under biased conditions so that chips with defects therein can be accelerated to failure, thereby avoiding their incorporation into a multichip integrated circuit module. Pursuant to the invention, special connection arrays are disposed in spacer blocks in a predetermined configuation on a substrate. The blocks define areas of the substrate which preferably accommodate a plurality of integrated circuit chips such that each chip is surrounded on each side by a spacer block. One or more connection arrays may be provided in each spacer block. The connection arrays have interconnection pads which in the final structure are accessible to an external probing device. Specific methods of fabrication are also disclosed.

Claims

1. A method for packing integrated circuit chips for testing, each of said integrated circuit chips to be packaged including at least one interconnection pad, said method comprising the steps of:

(a) disposing in predetermined pattern a plurality of spacer blocks on a substrate having a substantially flat upper surface, said spacer blocks being patterned to frame a multiplicity of distinct areas on said substrate'"'"'s upper surface, at least one of said plurality of spacer blocks including a connection array for applying one of a biasing signal, power signal, ground signal and clock signal to selected chip interconnection pads, said at least one connection array having at least one interconnection pad;

(b) disposing a plurality of integrated circuit chips on said substrate, each of said chips being disposed in one of said areas framed by said spacer blocks such that each chip is bounded on at least one side by a spacer block;

(c) employing an encapsulant to completely surround said chips and said spacer blocks and said upper surface of said substrate so that any space between said chips and said spacer blocks is filled by said encapsulant material;

(d) providing a plurality of via openings in said encapsulant, said openings being disposed over at least some of said chip interconnection pads and said connection array interconnection pads; and

(e) providing a pattern of electrical conductors above said encapsulant such that said conductors extend to said via openings so as to electrically connect selected chip interconnection pads and connection array interconnection pads through said openings.

2. The packaging method of claim 1, wherein said encapsulant employed in step (c) comprises low viscosity material and said method further includes curing said low viscosity material to a hardened, high viscosity encapsulant.

3. The packaging method of claim 2, wherein said curing step includes drying said employed encapsulant material.

4. The packaging method of claim 1, further comprising the step of lapping the top surface of said encapsulant to within two mils of the top surface of the chips, said lapped top surface of encapsulant being substantially parallel to the upper surface of said substrate.

5. The packaging method of claim 1, wherein said employed encapsulant comprises a solvent-sensitive material.

6. The packaging method of claim 5, further in combination with the step of burning-in said integrated circuit chips.

7. The combination method of claim 6, wherein said burning-in step includes applying one of a biasing signal, power signal, ground signal and clock signal to selected chip interconnection pads via said at least one connection array having a plurality of connection pads thereon.

8. The combination method of claim 7, further comprising the step of applying a high ambient temperature to said integrated circuit chip package for a predetermined length of time, said ambient temperature and said period of time being selected to sufficiently burn-in said plurality of integrated circuit chips.

9. The combination method of claim 8, further comprising the steps of testing said integrated circuit chips and recovering said integrated circuit chips from said package.

10. The combination method of claim 9, wherein said encapsulant is solvent-sensitive and said chip recovering step includes the steps of:

etching said pattern of electrical conductors provided above said encapsulant without damaging said integrated circuit chip interconnection pads; and

placing the package in a solvent to dissolve said solvent-sensitive encapsulant.

11. The combination method of claim 10, wherein said chip disposing step (b) includes affixing said plurality of integrated circuit chips to said substrate using a solvent-sensitive adhesive, and wherein said recovery step includes removing said solvent-sensitive adhesive from between said chips and said substrate, said chips being positionally maintained on said substrate by said plurality of spacer blocks.

12. The combination method of claim 11, further comprising the step of securing a cover over the top of said substrate with said integrated circuit chips positionally maintained thereon in said framed areas defined by said spacer blocks.

13. The combination method of claim 9, wherein said substrate includes a plurality of small holes disposed therein extending from the upper surface thereof to a lower surface of the substrate, said substrate holes being aligned substantially under said plurality of integrated circuit chips.

14. A method for packaging integrated circuit chips for burn-in, said method comprising the steps of:

(a) disposing a plurality of integrated circuit chips on a substantially flat upper surface of a substrate, each of said integrated circuit chips disposed on said substrate having at least one interconnection pad and each having multiple exposed surfaces when disposed on said substrate;

(b) disposing in a predetermined pattern a plurality of spacer blocks on said substrate such that each block is located at a side of at least one of said plurality of integrated circuit chips, at least one of said plurality of spacer blocks including a connection array for applying one of a biasing signal, power signal, ground signal and clock signal to at least one selected chip interconnection pad, each of said spacer blocks disposed on said substrate having multiple exposed surfaces and said at least one connection array having at least one interconnection pad;

(c) surrounding all exposed surfaces of said chips and said spacer blocks disposed on said upper surface of said substrate with an encapsulant such that space between said chips and said spacer blocks is filled by said encapsulant;

(d) providing a plurality of via openings in said encapsulant, said openings being disposed over at least some of said chip interconnection pads and said connection array interconnection pads; and

(e) providing a pattern of electrical conductors above said encapsulant such that said conductors extend to via openings so as to electrically connect selected chip interconnection pads and connection array interconnection pads through said openings.

15. The packaging method of claim 14, wherein said encapsulant employed in said step (c) comprises a low viscosity material and said method further includes curing said low viscosity material to a hardened, high viscosity encapsulant.

16. The packaging method of claim 15, wherein said curing step includes drying said employed encapsulant material.

17. The packaging method of claim 14, further comprising the step of lapping the top surface of said encapsulant to within 2 mils of the top surface of the chips, said lapped top surface of encapsulant being substantially parallel to the upper surface of said substrate.

18. The packaging method of claim 14, further in combination with the step of burning-in said integrated circuit chips.

19. The combination method of claim 18, wherein said burning-in step includes applying one of a biasing signal, power signal, ground signal and clock signal to selected chip interconnection pads via said at least one interconnection array having a plurality of interconnection pads thereon.

20. The combination method of claim 19, further comprising the step of increasing the ambient temperature surrounding said integrated circuit chip package for predetermined length of time, said ambient temperature and said period of time being selected to sufficiently burn-in said plurality of integrated circuit chips.

21. The combination method of claim 20, further comprising the steps of testing said integrated circuit chips and subsequently recovering said integrated circuit chips from said package.

22. The combination method of claim 21, wherein said encapsulant is solvent-sensitive and said chip removing step includes the steps of:

etching said pattern of electrical conductors provided above said encapsulant without damaging said integrated circuit chip interconnection pads; and

placing the package in a solvent to dissolve said solvent-sensitive encapsulant.

23. The combination method of claim 22, wherein said chip disposing step (a) includes affixing said plurality of integrated circuit chips to said substrate using a solvent-sensitive adhesive, and wherein said recovery step includes removing said solvent-sensitive adhesive from between said chips and said substrate, said chips being at least partially positionally maintained on said substrate by said plurality of spacer blocks.

24. A method for packaging, burning-in and retrieving integrated circuit chips, said method comprising the steps of:

(a) disposing a plurality of integrated circuit chips on a substrate having a flat upper surface, each of said integrated circuit chips disposed on said substrate having multiple exposed surfaces, one of said exposed surface having at least one interconnection pad;

(b) employing an encapsulant to surround all of said exposed chip surfaces such that space between said chips is completely filled by said encapsulant material and said encapsulant material covers said chips;

(c) providing a plurality of via openings in said encapsulant, said openings being disposed over at least some of said chip interconnection pads;

(d) providing a pattern of electrical conductors above said encapsulant such that said conductors extend to said via openings so as to electrically connect selected interconnection pads;

(e) applying at least one of a biasing signal, power signal, ground signal and clock signal to selected ones of said chip interconnection pads using said pattern of electrical conductors;

(f) burning-in said plurality of packaged integrated circuit chips; and

(g) exposing said burned-in integrated circuit chips by removing said pattern of electrical conductors on said encapsulant and dissolving said encapsulant.

25. The method of claim 24, wherein said encapsulant employed in said step (b) comprises a low viscosity material and said method further includes curing said low viscosity material to a hardened, high viscosity encapsulant.

26. The method of claim 25, wherein said employed encapsulant comprises a solvent-sensitive material.

27. The method of claim 24, wherein said burning-in step (f) includes applying a high ambient temperature to said integrated circuit chip package for a predetermined length of time, said ambient temperature and said period of time being selected to sufficiently burn-in said plurality of integrated circuit chips.

28. The method of claim 24, further comprising the step of recovering said burned-in integrated circuit chips exposed in said step (g).

29. The method of claim 28, wherein said chip disposing step (a) includes affixing said plurality of integrated circuit chips to said substrate using a solvent-sensitive adhesive, and wherein said chip recovering step includes removing said solvent-sensitive adhesive from between said chips and said substrate.

30. The method of claim 24, wherein said pattern of electrical conductors provided in said step (d) includes a predetermined footprint-type pattern on an upper surface of said encapsulant.

31. A method for retrieving package integrated circuit chips subsequent burn-in thereof, said packaged integrated circuit chips each have at least one interconnection pad and are disposed on a substantially flat upper surface of a substrate such that one surface of each chip is in opposing relation to said substrate upper surface, the remaining surfaces of said chips being covered with a solvent-sensitive encapsulant material such that said encapsulant covers all surfaces of each chip other than the chip surface in opposing relation to said substantially flat upper substrate surface and fills the space between said integrated circuit chips disposed on said substrate, a plurality of electrical conductors are further disposed so as to extend within said encapsulant and electrically connected selected chip interconnection pads, said retrieval method comprising the steps of:

(a) removing said pattern of electrical conductors from said encapsulant material;

(b) dissolving said solvent-sensitive encapsulant material so as to expose said plurality of integrated circuit chips disposed on the upper surface of said substrate; and

(c) removing said exposed integrated circuit chips from the upper surface of said substrate.

32. The chip retrieval method of claim 31, wherein said electrical conductor removing step (a) includes etching said pattern of electrical conductors from said encapsulant material without damaging said integrated circuit chip interconnection pads.

33. The chip retrieval method of claim 31, wherein said encapsulant material dissolving step (b) includes applying a solvent to said solvent=sensitive encapsulant material so as to dissolve said material surrounding said integrated circuit chips.

34. The chip retrieval method of claim 31, wherein said plurality of integrated circuit chips are fixed to said substantially flat upper surface of said substrate with a solvent-sensitive adhesive and wherein said exposed integrated circuit chip removing step (c) includes dissolving said solvent-sensitive adhesive affixing said integrated circuit chips to said substrate.