MOS folded source-coupled logic
First Claim
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1. An MOS logic circuit featuring reduced switching currents, the circuit comprising:
- a power bus having a substantially fixed voltage, which may be zero;
first and second MOS input transistors connected in a source-coupled arrangement and each having an input and an output;
first and second MOS output transistors connected in a common-gate arrangement and each having an input coupled to an output of an MOS input transistor;
a first constant current source coupling the power bus to the first MOS input transistor and to the first MOS output transistor; and
a second constant current source coupling the power bus to the second MOS input transistor and to the second MOS output transistor;
wherein overlap currents and displacement currents are prevented from generating large noise spikes.
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Abstract
In integrated circuitry having both analog and digital circuits fabricated on the same substrate, switching transients produced by the digital circuitry can propagate through the substrate and induce deleterious effects in the associated analog circuitry. Such switching transients are greatly minimized by a CMOS source-coupled current-steering differential logic topology. In the preferred embodiment, gain and level shifting functions are merged, and connections to the power bus are made through constant current sources.
69 Citations
23 Claims
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1. An MOS logic circuit featuring reduced switching currents, the circuit comprising:
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a power bus having a substantially fixed voltage, which may be zero; first and second MOS input transistors connected in a source-coupled arrangement and each having an input and an output; first and second MOS output transistors connected in a common-gate arrangement and each having an input coupled to an output of an MOS input transistor; a first constant current source coupling the power bus to the first MOS input transistor and to the first MOS output transistor; and a second constant current source coupling the power bus to the second MOS input transistor and to the second MOS output transistor; wherein overlap currents and displacement currents are prevented from generating large noise spikes. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A mixed mode integrated circuit comprising:
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a substrate; one or more analog circuits fabricated on said substrate; and one or more digital circuits fabricated on said substrate; at least one of said digital circuits comprising; a power bus having a substantially fixed voltage, which may be zero; first and second input transistors connected in a source-coupled arrangement and each having an input and an output; first and second output transistors connected in a common-gate arrangement and each having an input coupled to an output of an input transistor; a first constant current source coupling the power bus to the first input transistor and to the first output transistor; and a second constant current source coupling the power bus to the second input transistor and to the second output transistor. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. An MOS logic circuit featuring reduced switching currents, the circuit comprising:
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a power bus having a substantially fixed voltage, which may be zero; first and second MOS transistors connected in a source-coupled arrangement and each having an input and an output; third and fourth MOS transistors connected in a source-coupled arrangement, the drain of the third MOS transistor being connected to its gate and to the drain of the first MOS transistor, the drain of the fourth MOS transistor being connected to its gate and to the drain of the second MOS transistor, the sources of the first and second MOS transistors being coupled to the sources of the third and fourth MOS transistors by a path that includes a first constant current source; a second constant current source coupling the power bus to the drain of the first MOS transistor; a third constant current source coupling the power bus to the drain of the second MOS transistor; wherein overlap currents and displacement currents are prevented from generating large noise spikes.
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23. In a method of operating analog and digital circuitry on the same substrate, an improvement comprising operating at least a portion of the digital circuitry with a constant supply current by implementing said portion using differential circuitry and switching between constant current sources with each differential pair.
Specification