Programmable digital signal delay device and its use for a error correction code device

• US 5,150,066 A
• Filed: 05/30/1990
• Issued: 09/22/1992
• Est. Priority Date: 05/30/1989
• Status: Expired due to Term

• Current Assignee: Entropic Communications Incorporated (Maxlinear Incorporated)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Butel, Pascal, Ferrier, Joel, Dahiot, Alain
• Primary Examiner(s): Miller, Stanley D.
• Assistant Examiner(s): PHAN, TRONG Q
• Application Number:
  US07/530,712
• Time in Patent Office: 846 Days
• Field of Search: 371/31, 371/67, 371/69, 371/62, 307/590, 307/595, 307/596, 307/597, 307/602, 307/603, 307/605, 328/55, 328/63, 328/72
• US Class Current: 327/276
• CPC Class Codes: G06F 2205/104 Delay lines
• CPC Class Codes: G06F 5/10 having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory G06F5/065 takes precedence

Abstract

A programmable digital signal delay device for delaying a digital serial input signal SIN by a period τ=M.H. (where M is an integer H is the bit rate) and transforms SIN into a delayed output signal SOUT having the same bit rate, the number M being programmable in steps. The device includes an input register (4), a RAM (6) whose r bit locations contain p bits, an output register (8) and means for controlling the RAM which are formed by a decoder (11) which receives the number M, a cyclic counter (12) which receives a programming number N (or n) from the decoder whereby it cyclically addresses the RAM, and a sequencer (13) which supplies the RAM with the write and read control signals.

Claims

1. A delay device for delaying a digital serial input signal SIN by a programmable integer number M of periods H, so by a time τ

=M.H, and for transforming it into a delayed digital serial output signal SOUT having the same bit rate as SIN, comprising an at least one-bit input register, a random access memory (RAM) connected to the input register and having a plurality r of memory locations each location containing an integer number p of bits which is at least equal to 1, an at least one-bit output register connected to the random access memory, and means for controlling the RAM including a decoder which receives the number M in digital form on an input bus, and produces a programming number N on an output bus, a cyclic counter connected to the decoder and the RAM which receives, from the output bus of the decoder, the programming number N or its principal part n and cyclically addresses the RAM, and a sequencer connected to the cyclic counter for receiving a write/read control signal from the cyclic counter and supplying the RAM with write and read control signals.

2. A delay device as claimed in claim 1, in which the decoder comprises a subtractor for subtracting a number q from M wherein q is related to an internal delay expressed as an integer number of periods H intrinsically induced by said input and output registers and the RAM during operation.

3. A delay device as claimed in claim 2, in which the RAM is organized in p-bit words, p being equal to 2 or a multiple of 2, and said input register comprises a serial input and p parallel outputs, and said output register comprises p parallel inputs and one serial output;

and also comprising a programmable shift register connected to the input register which receives the least significant bits from the output bus of the decoder and which supplies a number of shift bits 1 so that np+l-1=N, said decoder being constructed to apply said principal part n of the programming number N to said cyclic counter.

4. A delay device as claimed in claim 3, in which said programmable shift register comprises a series connection of a p-bit shift register having a serial input and p parallel outputs, and a multiplexer having p parallel inputs and a serial output.

5. A delay device as claimed in claim 3, in which said shift register is programmable in steps of 1 bit and has a length is at least equal to p+q-1, and said decoder comprises detection means for detecting whether the number M is greater than or equal to or smaller than p+q, and control means responsive to the detection means for switching, if M is smaller than p+q, the least significant input bits of the decoder simultaneously to a simplified internal decoding device of the decoder, and the serial data output of the programmable shift register to the output of said delay device.

6. A delay device as claimed in claim 1, comprising a single integrated circuit.

7. The use of the delay device as claimed in claim 1 for an error correction code device in order to realize delays greater than 500 bit periods with a bit rate of about 40 MHz.

8. The use of the delay device as claimed in claim 1 for delaying one or more image lines encoded in digital form.

9. The use of the delay device as claimed in claim 4 for delaying one or more image lines encoded in digital form.