Multiplexed sigma-delta A/D converter

• US 5,150,120 A
• Filed: 01/03/1991
• Issued: 09/22/1992
• Est. Priority Date: 01/03/1991
• Status: Expired due to Term

• Current Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Yunus, Mohammad
• Primary Examiner(s): Logan, Sharon D.
• Application Number:
  US07/637,047
• Time in Patent Office: 628 Days
• Field of Search: 341/143, 341/155, 341/122, 341/141, 375/125, 375/26
• US Class Current: 341/143
• CPC Class Codes: H03M 3/43 the quantiser being a single bit one
• CPC Class Codes: H03M 3/454 with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage
• CPC Class Codes: H03M 3/47 using time-division multiplexing

Abstract

A sigma-delta analog-to-digital converter employs multiplexed single-loop modulators in parallel and respectively phased time-divided clocks. The parallel modulators have the effect of producing digital output at a high sampling frequency that is a multiple of the phased switching frequencies applied to the modulator circuits. In one preferred embodiment, four second-order sigma-delta modulators are driven in clocked phased sequence and combined by a multiplexor circuit. Another embodiment employs second-order modulators using RC integrators. A further embodiment replaces the multiplexor with an adder when in-phase modulator clocks are used, and the adder also acts as a simple low pass filter.

Claims

1. A sigma-delta analog-to-digital converter comprising:

a plurality N of sigma-delta modulators arranged in parallel having an analog input signal applied thereto and being controlled by a respective modulator clock at a given modulator sampling frequency and providing a respective modulator digital output signal;

signal combining means coupled to said plurality N of sigma-delta modulators for combining the modulator digital output signals from said modulators in phased sequence to form an overall digital output signal, wherein said overall output digital signal has an effective sampling frequency that is a multiple of N times the sampling frequency of the individual modulators; and

filtering means for filtering quantization noise from said overall digital output signal.

2. A sigma-delta analog-to-digital converter according to claim 1, wherein said sigma-delta modulators are second-order modulators each containing two integrators in sequence and a comparator/latch circuit as an internal A/D converter.

3. A sigma-delta analog-to-digital converter according to claim 2, wherein said second-order modulators are switched-capacitor type modulators.

4. A sigma-delta analog-to-digital converter according to claim 2, wherein said second-order modulators have respective RC integrators.

5. A sigma-delta analog-to-digital converter according to claim 1, wherein said signal combining means is a multiplexor circuit having a plurality of phased multiplexor clocks applied thereto each corresponding to a respective one of the plurality N of sigma-delta modulators.

6. A sigma-delta analog-to-digital converter according to claim 1, wherein said modulator clocks are in phased sequence with each other.

7. A sigma-delta analog-to-digital converter according to claim 1 wherein said modulator clocks are equal to and in phase with each other.

8. A sigma-delta analog-to-digital converter according to claim 1, wherein said filtering means is a digital low pass filter.

9. A sigma-delta analog-to-digital converter according to claim 1, wherein said signal combining means is an adder for adding the modulator digital output signals together and providing said overall digital output signal.

10. A sigma-delta analog-to-digital converter according to claim 9, wherein said adder also serves as said filtering means by outputting a digital sum signal.

11. A sigma-delta analog-to-digital converter comprising:

a plurality N of sigma-delta modulators arranged in parallel having an analog input signal applied thereto and being controlled by a respective modulator clock at a given modulator sampling frequency and providing a respective modulator digital output signal, wherein said sigma-delta modulators are second-order modulators each containing two integrators in sequence and a comparator/latch circuit as an internal A/D converter;

signal combining means coupled to said plurality N of sigma-delta modulators for combining the modulator digital output signals from said modulators in phased sequence to form an overall digital output signal, wherein said overall digital output signal has an effective sampling frequency that is a multiple of N times the sampling frequency of the individual modulators; and

filtering means for filtering quantization noise from said overall output digital signal.

12. A sigma-delta analog-to-digital converter according to claim 11, wherein said plurality N is four in number, and said overall digital output signal has an effective sampling rate that is four times the sampling frequency of the individual modulators.

13. A sigma-delta analog-to-digital converter according to claim 11, wherein said second-order modulators are switched-capacitor type modulators.

14. A sigma-delta analog-to-digital converter according to claim 11, wherein said second-order modulators have respective RC integrators.

15. A sigma-delta analog-to-digital converter according to claim 11, wherein said signal combining means is a multiplexor circuit having a plurality of phased multiplexor clocks applied thereto each corresponding to a respective one of the plurality N of sigma-delta modulators.

16. A sigma-delta analog-to-digital converter according to claim 11, wherein said modulator clocks are in phased sequence with each other.

17. A sigma-delta analog-to-digital converter according to claim 11, wherein said modulator clocks are equal to and in phase with each other.

18. A sigma-delta analog-to-digital converter according to claim 11, wherein said filtering means is a digital low pass filter.

19. A sigma-delta analog-to-digital converter according to claim 17, wherein said signal combining means is an adder for adding the modulator digital output signals together and providing said overall digital output signal.

20. A sigma-delta analog to-digital converter according to claim 19, wherein said adder also serves as said filtering means by a digital sum signal.