Parallel pulse processing and data acquisition for high speed, low error flow cytometry
First Claim
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1. Apparatus for pulse processing and data acquisition from a plurality of detectors generating asynchronous event pulses from a single event, comprising:
- a plurality of parallel input channels, each of which receives one of the event pulses from a respective detector;
pulse digitization means in each channel for digitizing the event pulse received in the channel;
a channel FIFO buffer in each channel connected to the respective pulse digitization means;
a common data bus connected to all the FIFO buffers;
central control means external to the channels connected to each channel for providing a synchronizing timing signal to the respective pulse digitization means in each channel in response to a start signal from at least one of the channels to synchronize pulse digitization in each channel with detection of the event by the respective detector and to digitize each pulse on each channel substantially immediately after the pulse is input on the channel;
a bus controller connected to the data bus and to the control means for transferring correlated data from the FIFO buffers to the data bus following an actuation signal from the control means, the transferred data being correlated to the event.
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Abstract
A digitally synchronized parallel pulse processing and data acquisition system for a flow cytometer has multiple parallel input channels with independent pulse digitization and FIFO storage buffer. A trigger circuit controls the pulse digitization on all channels. After an event has been stored in each FIFO, a bus controller moves the oldest entry from each FIFO buffer onto a common data bus. The trigger circuit generates an ID number for each FIFO entry, which is checked by an error detection circuit. The system has high speed and low error rate.
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Citations
25 Claims
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1. Apparatus for pulse processing and data acquisition from a plurality of detectors generating asynchronous event pulses from a single event, comprising:
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a plurality of parallel input channels, each of which receives one of the event pulses from a respective detector; pulse digitization means in each channel for digitizing the event pulse received in the channel; a channel FIFO buffer in each channel connected to the respective pulse digitization means; a common data bus connected to all the FIFO buffers; central control means external to the channels connected to each channel for providing a synchronizing timing signal to the respective pulse digitization means in each channel in response to a start signal from at least one of the channels to synchronize pulse digitization in each channel with detection of the event by the respective detector and to digitize each pulse on each channel substantially immediately after the pulse is input on the channel; a bus controller connected to the data bus and to the control means for transferring correlated data from the FIFO buffers to the data bus following an actuation signal from the control means, the transferred data being correlated to the event. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A method for pulse processing and data acquisition from a plurality of asynchronous pulses generated by a single event from a plurality of detectors comprising:
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inputting an event pulse onto each of a plurality of parallel input channels; digitizing each event pulse on each channel substantially immediately after inputting the pulse on the channel and synchronously with detection of the event by an associated detector; storing the digitized event in a FIFO buffer on each channel; transferring correlated stored digitized event data about a single event from all the FIFO buffers onto a common data bus. - View Dependent Claims (19, 20, 21, 22, 23, 24)
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25. Apparatus for generating a trigger pulse, comprising:
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a comparator having its input connected to a start signal; a leading edge detector having its input connected to the output of the comparator; an input gate having an input connected to the output of the leading edge detector and another input connected to a block signal; a first flip-flop having its set input connected to the output of the input gate; a second flip-flop having its set input connected to the output of the first flip/flop and is clear input connected to the output of the comparator; a minimum event separation timer connected to the clear input of the first flip/flop; a minimum event width timer having an input connected to the output of the second flip/flop; an OR gate having a first input connected to the output of the second flip/flop and a second input connected to the output of the minimum event timer and its output connected to the input of the minimum event separation timer; wherein the outputs of the second flip/flop, the OR gate, and the minimum event width timer can be used as trigger pulses.
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Specification