Process for metallizing integrated circuits with electrolytically-deposited copper

• US 5,151,168 A
• Filed: 09/24/1990
• Issued: 09/29/1992
• Est. Priority Date: 09/24/1990
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Cathey, David A, Gilton, Terry L., Tuttle, Mark E.
• Primary Examiner(s): TUFARIELLO, THOMAS
• Application Number:
  US07/587,302
• Time in Patent Office: 736 Days
• Field of Search: 204/15, 204/52.1
• US Class Current: 205/123
• CPC Class Codes: H01L 21/2885 using an external electrical current, i.e. electro-deposition
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs

Abstract

A masked, conformal electrodeposition process for copper metallization of integrated circuits. The process is considerably less complex than other metallization processes utilizing electrodeposition, and provides excellent step coverage for sub-micron contact openings. Full-step coverage has been obtained with the process for contact openings as small as 0.5 microns in diameter. The process begins with the blanket sputter or LPCVD deposition of a thin conductive barrier layer of a material such as titanium nitride, titanium-tungsten or nitrided titanium-tungsten. A photoresist reverse image of the maskwork that normally would be used to etch the metallization pattern on the circuitry is created on the wafer on top of the barrier layer. As an option, the reverse image of the desired metallization pattern may be created by etching a dielectric material layer such as silicon dioxide or silicon nitride, using a photoresist reverse image as a template. The wafer is then transferred to an electrolytic bath, preferably with a pH of 13.5, in which copper is complexed with EDTA molecules. Metallic copper is deposited on the barrier layer where it is not covered by photoresist. At current densities of less than 1 milliamp/cm², the process will automatically fill contact/via openings to a uniform thickness which is independent of the depth of the opening. Following electrodeposition of the metallization layer to the desired thickness, the wafer is removed from the bath, and the photoresist or dielectric material reverse-pattern mask is stripped. At this point, an optional corrosion-resistant metal layer may be galvanically plated on the surface of the copper layer. Finally, portions of the barrier layer that were exposed by removal of the resist are then removed with either a wet or a dry etch.

Claims

1. A process for metallizing an integrated circuit chip with copper comprising the following sequence of steps:

forming electrical contact openings in a dielectric layer on the chip;

deposition of a conductive barrier layer on the surface of the chip;

creating a dielectric material mask on top of the barrier layer, said mask being a reverse image of the desired metallization pattern;

submersing the chip in an electrolytic bath having copper ions complexed with EDTA molecules, such that metallic copper is deposited to a desired thickness on portions of the barrier layer that are not covered by said dielectric material mask;

stripping the dielectric material mask; and

removal of those portions of the barrier layer that were exposed by removal of the dielectric material mask.

2. The process for metallizing of claim 1, wherein said electrolytic bath is a basic solution having a pH within a range of 6.5 to 14.0.

3. The process for metallizing of claim 2, wherein said electrolytic bath is a basic solution having a pH within a range of 13.0 to 14.0.

4. The process for metallizing of claim 1, wherein said electrolytic bath is maintained at a temperature within a range of 20°

C. to 35°

C.

5. The process for metallizing of claim 4, wherein said electrolytic bath is maintained at a temperature substantially equal to 25°

C.

6. The process for metallizing of claim 1, wherein current densities within the chip are maintained below 1.0 milliamp/cm².

7. The process of claim 1, wherein said barrier layer consists of titanium nitride.

8. The process of claim 1, wherein said barrier layer consists of titanium-tungsten.

9. The process of claim 1, wherein said barrier layer consists of nitrided titanium-tungsten.

10. The process of claim 1, wherein said dielectric material mask consists of photoresist.

11. The process of claim 10, wherein said photoresist is UV irradiated and baked to stabilize it so that it will not dissolve in a highly-basic electrolytic bath.

12. The process of claim 11, wherein stripping of the photoresist dielectric material mask is accomplished with a non-aqueous photoresist stripping compound which is essentially free of phenol compounds and halogenated hydrocarbon compounds and which consists essentially of:

a) from about 2 percent to about 98 percent by weight of an amine compound selected from the group consisting of compounds having the formula (H₂)_N --(H₂ C)_N --Y--(H₂ C)_M --Z, where N and M are each independently an integer ranging from 1-5 inclusive;

Y is either --O-- or --NH--; and

Z is --H, --OH or --NH₂ ; and

mixtures thereof, and;

b) from about 98 to about 2 percent by weight of an organic polar solvent selected from the group consisting of N-methyl-2-pyrrolidinone, tetrahydrofurfuryl alcohol, isophorone, dimethyl sulfoxide, dimethyl adipate, dimethyl glutarate, sulfolane, gamma -butyrolactone, N,N-dimethylacetamide and mixtures thereof.

13. The process of claim 1, wherein said dielectric material mask consists of silicon dioxide

14. The process of claim 1, wherein said dielectric material mask consists of silicon nitride.

15. The process of claim 1, which further comprises the step of galvanically depositing an optional corrosion-resistant metal layer on the surface of the deposited copper layer following electrodeposition of copper and prior to stripping the dielectric material layer mask.

16. The process of claim 15, wherein said corrosion-resistant metal is gold.

17. The process of claim 15, wherein said corrosion-resistant metal is nickel.

18. The process of claim 15, wherein said corrosion-resistant metal is palladium.

19. The process of claim 1, wherein the copper ions in said electrolytic bath are provided by copper sulfate.

20. The process of claim 19, wherein said copper sulfate has a concentration within a range of 0.01 to 0.07 molar.

21. The process of claim 20, wherein said copper sulfate has a concentration substantially equal to 0.035 molar.

22. The process of claim 1, wherein the EDTA molecules in said electrolytic bath are provided by a hydrolyzed salt.

23. The process of claim 22, wherein the salt is Na₄ EDTA.

24. The process of claim 23, wherein the concentration of said salt is within a range of 0.02 to 0.14 molar.

25. The process of claim 24, wherein the concentration of said salt is substantially equal to 0.070 molar.