CMOS logic circuit with output coupled to multiple feedback paths and associated method
First Claim
Patent Images
1. A TTL to CMOS input buffer circuit comprising:
- level shifting means which includes an input terminal and an output node for receiving at the input terminal an input signal at a TTL logic voltage level and for providing at the output node an output signal at a CMOS logic voltage level, the output signal being a logically inverted version of the input signal;
first means for speeding a transition of the output signal from a low CMOS voltage level to a high CMOS voltage level; and
second means, operative throughout a transition of the output signal from the high CMOS voltage level to the low CMOS voltage level, for deactivating said first means when the output signal is static at the high CMOS voltage level and for maintaining said first means in a deactivated state throughout a transition from the high CMOS voltage level to the low CMOS voltage level.
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Abstract
A TTL to CMOS input buffer circuit is provided which includes a level shifting circuit including an input terminal and an output node for receiving at the input terminal an input signal at a TTL logic voltage level and for providing at the output node an output signal at a CMOS logic voltage level, the output signal being a logically inverted version of the input signal; and a first circuit for speeding a transition of the output signal from a low CMOS voltage level to a high CMOS voltage level; and a second circuit for preventing the first circuit from interfering with a transition of the output signal from the high CMOS voltage level to the low CMOS voltage level.
41 Citations
25 Claims
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1. A TTL to CMOS input buffer circuit comprising:
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level shifting means which includes an input terminal and an output node for receiving at the input terminal an input signal at a TTL logic voltage level and for providing at the output node an output signal at a CMOS logic voltage level, the output signal being a logically inverted version of the input signal; first means for speeding a transition of the output signal from a low CMOS voltage level to a high CMOS voltage level; and second means, operative throughout a transition of the output signal from the high CMOS voltage level to the low CMOS voltage level, for deactivating said first means when the output signal is static at the high CMOS voltage level and for maintaining said first means in a deactivated state throughout a transition from the high CMOS voltage level to the low CMOS voltage level. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A TTL to CMOS input buffer circuit comprising:
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a CMOS inverter circuit which includes an input terminal and an output node for receiving at the input terminal an input signal at a TTL logic voltage level and for providing at the output node an output signal at a CMOS logic voltage level, the output signal being a logically inverted version of the input signal; a voltage supply; a first pull-up transistor coupled to the output node; first control means responsive to the output signal for providing a first logical control signal to a gate of the first pull-up transistor; a second pull-up transistor coupled between the voltage supply and the first pull-up transistor; and second control means responsive to the output signal for providing a second logical control signal to a gate of the second pull-up transistor; and delay means for delaying an occurrence of a change in a logical state of the second control signal relative to an occurrence of a corresponding change in a logical state of the first control signal. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17)
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18. A TTL to CMOS input buffer circuit comprising:
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a CMOS inverter circuit which includes an input terminal and an output node for receiving at the input terminal an input signal at a TTL logic voltage level and for providing at the output node an output signal at a CMOS logic voltage level, the output signal being a logically inverted version of the input signal; a PMOS current source transistor coupled in series with a PMOS transistor of said CMOS inverter circuit; a voltage supply; a first PMOS pull-up transistor including a drain coupled to the output node; first feedback means, responsive to the output signal and including at least one inverter circuit, for providing a first logical control signal to a gate of the first PMOS pull-up transistor; a second PMOS pull-up transistor including a source coupled to the voltage supply and a drain coupled to a source of the first pull-up transistor; and second feedback means, responsive to the output signal, for providing a second logic control signal to a gate of the second pull-up PMOS transistor and for delaying an occurrence of a change in a logical state of the second control signal relative to an occurrence of a corresponding change in a logical state of the first control signal.
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19. A method for shifting signals from TTL logic voltage levels to CMOS logic voltage levels using a CMOS inverter circuit which includes an input terminal and an output node and which includes a voltage supply and a pull-up transistor including source and drain terminals coupled between the voltage supply and the output node, the method comprising the steps of:
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receiving a respective input signal at TTL logic voltage levels at the input terminal; providing a respective output signal at CMOS logic voltage levels at the output node, the respective output signal being a respective logically inverted version of the respective received input signal; providing the output signal static at a high CMOS voltage level; deactivating the pull-up transistor while the output signal is static at the high CMOS voltage level; transitioning the output signal from the static high CMOS voltage level to a low CMOS voltage level and then transitioning the output signal back to the high CMOS voltage level; in the course of the step of transitioning the output signal from a low CMOS voltage level back to a high CMOS voltage level, pulling up the voltage level of such respective output signal using the pull-up transistor; and maintaining the pull-up transistor in a deactivated state throughout the step of transitioning the output signal from the static high CMOS voltage level to a low CMOS voltage level. PG,24 - View Dependent Claims (20, 21)
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22. A method for transitioning CMOS logic level output signals between high and low CMOS voltage levels comprising the steps of:
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providing the output signal at a static CMOS high voltage level; deactivating an output pull-up transistor while the output signal is in the static CMOS high voltage level; transitioning the output signal from the high CMOS voltage level to a low CMOS voltage level and back to the high CMOS voltage level; in the course of the step of transitioning the output signal from a low CMOS voltage level to the high CMOS voltage level, pulling up the voltage level of such respective output signal using the output pull-up transistor; and maintaining the pull-up transistor in a deactivated state throughout the step of transitioning the output signal from the static high CMOS voltage level to a low CMOS voltage level. - View Dependent Claims (23, 24)
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25. A TTL to CMOS input buffer circuit comprising:
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level shifting means which includes an input terminal and an output node for receiving at the input terminal an input signal at a TTL logic voltage level and for providing at the output node an output signal at a CMOS logic voltage level, the output signal being a logically inverted version of the input signal; first means for speeding a transition of the output signal from a low CMOS voltage level to a high CMOS voltage level; and second means for deactivating said first means when the output signal is static at the high CMOS voltage level and for maintaining said first means in a deactivated state throughout a transition of the output signal from the high CMOS voltage level to the low CMOS voltage level.
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Specification