Multiplier circuit
First Claim
1. A multiplier circuit having a first pair and a second pair of input terminals and first and second output terminals comprising:
- at least first and second multiplier cells;
the second multiplier cell having a lower circuit level and a downstream upper circuit level, a first pair of input terminals of the second multiplier cell assigned to the upper circuit level thereof and connected to the first pair of input terminals of the multiplier circuit, and a second pair of input terminals assigned to the lower circuit level thereof and connected to the second pair of input terminals of the multiplier circuit, the second multiplier cell connected to a first voltage terminal, the first output terminal of the multiplier circuit connected via a first resistance element to a second voltage terminal, and the second output terminal of the multiplier circuit connected to the second voltage terminal via a second resistance element, the first multiplier cell having a lower circuit level and a downstream upper circuit level, a first pair of input terminals of the first multiplier cell assigned to the upper circuit level thereof and connected to the second pair of input terminals of the second multiplier cell, and a second pair of input terminals of the first multiplier cell, assigned to the lower circuit level thereof and connected to the first pair of input terminals of the second multiplier cell, the first multiplier cell connected to the first voltage terminal, and a first output terminal of the second multiplier cell and a first output terminal of the first multiplier cell connected together and forming the first output terminal of the multiplier circuit, and a second output terminal of the second multiplier cell and a second output terminal of the first multiplier cell connected together and forming the second output terminal of the multiplier circuit.
1 Assignment
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Accused Products
Abstract
The invention relates to a multiplier circuit which is constructed from two multiplier cells according to the prior art. The disadvantage of different signal transit times in the emitter followers and the differential stages for the two input signals to be treated identically is overcome by arranging the transmission paths symmetrically. The limiting frequency of the arrangement according to the invention is no longer limited by the phase error, but solely by the switching time of the bipolar transistors employed, and is therefore higher than in a multiplier circuit according to the prior art. For all frequencies below the limiting frequency, given a phase difference of 90° the output signal lies exactly in the middle of the modulation range.
58 Citations
8 Claims
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1. A multiplier circuit having a first pair and a second pair of input terminals and first and second output terminals comprising:
- at least first and second multiplier cells;
the second multiplier cell having a lower circuit level and a downstream upper circuit level, a first pair of input terminals of the second multiplier cell assigned to the upper circuit level thereof and connected to the first pair of input terminals of the multiplier circuit, and a second pair of input terminals assigned to the lower circuit level thereof and connected to the second pair of input terminals of the multiplier circuit, the second multiplier cell connected to a first voltage terminal, the first output terminal of the multiplier circuit connected via a first resistance element to a second voltage terminal, and the second output terminal of the multiplier circuit connected to the second voltage terminal via a second resistance element, the first multiplier cell having a lower circuit level and a downstream upper circuit level, a first pair of input terminals of the first multiplier cell assigned to the upper circuit level thereof and connected to the second pair of input terminals of the second multiplier cell, and a second pair of input terminals of the first multiplier cell, assigned to the lower circuit level thereof and connected to the first pair of input terminals of the second multiplier cell, the first multiplier cell connected to the first voltage terminal, and a first output terminal of the second multiplier cell and a first output terminal of the first multiplier cell connected together and forming the first output terminal of the multiplier circuit, and a second output terminal of the second multiplier cell and a second output terminal of the first multiplier cell connected together and forming the second output terminal of the multiplier circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
- at least first and second multiplier cells;
Specification