Fermi threshold silicon-on-insulator field effect transistor

• US 5,151,759 A
• Filed: 01/25/1991
• Issued: 09/29/1992
• Est. Priority Date: 03/02/1989
• Status: Expired due to Term

• Current Assignee: Thunderbird Technologies Incorporated
• Original Assignee: Thunderbird Technologies Incorporated
• Inventors: Vinal, Albert W.
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US07/646,829
• Time in Patent Office: 613 Days
• Field of Search: 357/23.3, 357/23.7, 357/23.12, 357/23.14, 357/4
• US Class Current: 257/348
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/7836 with a significant overlap between the lightly doped extension and the gate electrode H01L29/7834, H01L29/7835 take precedence
• CPC Class Codes: H01L 29/7838 without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs

Abstract

A Silicon-on-Insulator (SOI) field effect transistor (FET) operates in the enhancement mode without requiring inversion by setting the device'"'"'s threshold voltage to twice the Fermi potential of the thin semiconductor layer in which the transistor is fabricated. The FET, referred to as a Fermi Threshold SOI FET or Fermi SOI FET, has a threshold voltage which is independent of oxide thickness, channel length, drain voltage and substrate channel doping. The vertical electric field in the substrate channel becomes zero, thereby maximizing carrier mobility, and minimizing hot electron effects. The thin silicon layer in which the devices are formed is sufficiently thick such that the channel is not fully depleted at pinch-off. A high speed device, substantially independent of device dimensions is thereby provided, which may be manufactured using relaxed groundrules, to provide low cost, high yield devices.

Temperature dependence of threshold voltage may also be eliminated by providing a semiconductor gate contact which neutralizes the effect of substrate contact potential. Multiple gate devices may be provided. An accelerator gate, adjacent the drain, may further improve performance.

Claims

1. A field effect transistor comprising:

a thin semiconductor layer having a first surface and a second surface opposite said first surface;

source and drain regions of first conductivity type in said thin semiconductor layer;

a channel substrate of second conductivity type, in said thin semiconductor layer at said second surface, between said source and drain regions;

a channel of said first conductivity type in said thin semiconductor layer at said first surface, between said source and drain regions, said channel having a predetermined depth from said first surface;

a gate insulating layer on said thin semiconductor layer at said first surface adjacent said channel, at least one of the source doping, source depth, drain doping, drain depth, channel substrate doping, channel substrate depth, channel doping and channel depth being selected to produce zero static electric field perpendicular to said first surface at said first surface between said channel and said gate insulating layer; and

source, drain and gate contacts for electrically contacting said source and drain regions and said gate insulating layer, respectively.

2. The field effect transistor of claim 1 wherein said channel substrate is doped at a first dopant density, wherein said channel is doped at a second dopant density, and wherein at least one of said first and second dopant densities and said predetermined depth are selected to product zero static electric field perpendicular to said first surface at said first surface between said channel and said gate insulating layer.

3. The field effect transistor of claim 1 further comprising:

an insulating layer on said thin semiconductor layer at said second surface; and

a substrate on said insulating layer, to thereby produce a semiconductor-on-insulator field effect transistor.

4. The field effect transistor of claim 1 wherein said thin semiconductor layer, said source and said drain are all a first predetermined thickness, and wherein said channel substrate and said channel are, in combination, said first predetermined thickness.

5. The field effect transistor of claim 4 wherein said first predetermined thickness is sufficiently thick such that said channel substrate is not fully depleted at pinch-off.

6. The field effect transistor of claim 1 wherein said channel comprises a plurality of channels separated from one another by rail regions;

and wherein said gate contact comprises a plurality of gate contacts, a respective one of which overlies a respective one of said plurality of channels.

7. The field effect transistor of claim 3 wherein said channel substrate comprises a first semiconductor material in monocrystalline form, and being doped at a first doping density;

wherein said gate contact comprises said first semiconductor material of said second conductivity type and being doped at said first dopant density; and

wherein said field effect transistor further comprises a substrate contact for electrically contacting said substrate.

8. The field effect transistor of claim 1 wherein said thin semiconductor layer comprises a thin layer of monocrystalline silicon.

9. A field effect transistor comprising:

a thin semiconductor layer having a first surface and a second surface opposite said first surface;

source and drain regions of first conductivity type in said thin semiconductor layer;

a channel substrate of second conductivity type, in said thin semiconductor layer at said second surface, between said source and drain regions;

a channel of said first conductivity type in said thin semiconductor layer at said first surface, between said source and drain regions, said channel having a predetermined depth from said first surface;

a gate insulating layer on said thin semiconductor layer at said first surface adjacent said channel, at least one of the source doping, source depth, drain doping, drain depth, channel substrate doing, channel substrate depth, channel doping and channel depth being selected to produce a threshold voltage for said field effect transistor which is twice the Fermi potential of said channel substrate; and

source, drain and gate contacts for electrically contacting said source and drain regions and said gate insulating layer, respectively.

10. The field effect transistor of claim 9 wherein said channel substrate is doped at a first dopant density, wherein said channel is doped at a second dopant density, and wherein at least one of said first and second dopant densities and said predetermined depth are selected to produce a threshold voltage for said field effect transistor which is twice the Fermi potential of said channel substrate.

11. The field effect transistor of claim 9 further comprising:

an insulating layer on said thin semiconductor layer at said second surface; and

a substrate on said insulating layer, to thereby produce a semiconductor-on-insulator field effect transistor.

12. The field effect transistor of claim 9 wherein said thin semiconductor layer, said source and said drain are all a first predetermined thickness, and wherein said channel substrate and said channel are, in combination, said first predetermined thickness.

13. The field effect transistor of claim 12 wherein said first predetermined thickness is sufficiently thick such that said channel substrate is not fully depleted at pinch-off.

14. The field effect transistor of claim 9 wherein said channel comprises a plurality of channels separated from one another by rail regions;

and wherein said gate contact comprises a plurality of gate contacts, a respective one of which overlies a respective one of said plurality of channels.

15. The field effect transistor of claim 11 wherein said channel substrate comprises a first semiconductor material in monocrystalline form, and being doped at a first doping density;

wherein said gate contact comprises said first semiconductor material of said second conductivity type and being doped at said first dopant density; and

wherein said field effect transistor further comprises a substrate contact for electrically contacting said substrate.

16. The field effect transistor of claim 9 wherein said thin semiconductor layer comprises a thin layer of monocrystalline silicon.

17. A field effect transistor comprising:

a thin semiconductor layer having a first surface and a second surface opposite said first surface;

source and drain regions of first conductivity type in said thin semiconductor layer;

a channel substrate of second conductivity type, in said thin semiconductor layer at said second surface, between said source and drain regions;

a channel of said first conductivity type in said thin semiconductor layer at said first surface, between said source and drain regions, said channel having a predetermined depth from said first surface and a predetermined length from said source to said drain;

a gate insulating layer on said thin semiconductor layer at said first surface adjacent said channel and having a predetermined thickness, at least one of the source doping, source depth, drain doping, drain depth, channel substrate doping, channel substrate depth, channel doping and channel depth being selected to produce a threshold voltage for said field effect transistor which is independent of said predetermined length and said predetermined thickness; and

source, drain and gate contacts for electrically contacting said source and drain regions and said gate insulating layer, respectively.

18. The field effect transistor of claim 17 wherein said channel substrate is doped at a first dopant density, wherein said channel is doped at a second dopant density, and wherein at least one of said first and second dopant densities and said predetermined depth are selected to produce a threshold voltage for said field effect transistor which is independent of said predetermined length and said predetermined thickness.

19. The field effect transistor of claim 17 further comprising:

an insulating layer on said thin semiconductor layer at said second surface; and

a substrate on said insulating layer, to thereby produce a semiconductor-on-insulator field effect transistor.

20. The field effect transistor of claim 19 wherein said channel substrate comprises a first semiconductor material in monocrystalline form, and being doped at a first doping density;

wherein said gate contact comprises said first semiconductor material of said second conductivity type and being doped at said first dopant density; and

wherein said field effect transistor further comprises a substrate contact for electrically contacting said substrate.

21. The field effect transistor of claim 17 wherein said thin semiconductor layer, said source and said drain are all a first predetermined thickness, and wherein said channel substrate and said channel are, in combination, said first predetermined thickness.

22. The field effect transistor of claim 21 wherein said first predetermined thickness is sufficiently thick such that said channel substrate is not fully depleted at pinch-off.

23. The field effect transistor of claim 17 wherein said channel comprises a plurality of channels separated from one another by rail regions;

and wherein said gate contact comprises a plurality of gate contacts, a respective one of which overlies a respective one of said plurality of channels.

24. The field effect transistor of claim 17 wherein said thin semiconductor layer comprises a thin layer of monocrystalline silicon.

25. A field effect transistor comprising:

a thin semiconductor layer having a first surface and a second surface opposite said first surface, said thin semiconductor layer having an intrinsic carrier concentration N_i at temperature T degrees Kelvin, and a dielectric constant e_s ;

source and drain regions of first conductivity type in said thin semiconductor layer;

a channel substrate of second conductivity type, in said thin semiconductor layer at said second surface, between said source and drain regions, and being doped at a first dopant density N_a ;

a channel of said first conductivity type in said thin semiconductor layer at said first surface between said source and drain regions, said channel being doped at a second dopant density which is a factor α

times said first dopant density N_a, said channel having a predetermined depth A from said first surface, with A being √

(2e_s φ

_s)/(qN_a α

(α

+1)), where φ

_s is (2KT/q)ln(N_a /N_i), q is equal to 1.6×

10^-19 coulombs, and K is equal to 1.3×

10^-23 Joules/°

Kelvin;

a gate insulating layer on said thin semiconductor layer at said first surface adjacent said channel; and

source, drain and gate contacts for electrically contacting said source and drain regions and said gate insulating layer, respectively.

26. The field effect transistor of claim 25 further comprising:

an insulating layer on said thin semiconductor layer at said second surface; and

a substrate on said insulating layer;

to thereby produce a semiconductor-on-insulator field effect transistor.

27. The field effect transistor of claim 26 wherein said channel substrate comprises a first semiconductor material in monocrystalline form, and being doped at said first doping density;

wherein said gate contact comprises said first semiconductor material of said second conductivity type in polycrystalline form and being doped at said first dopant density; and

wherein said field effect transistor further comprises a substrate contact for electrically contacting said substrate.

28. The field effect transistor of claim 25 wherein said thin semiconductor layer, said source and said drain are all a first predetermined thickness, and wherein said channel substrate and said channel are, in combination, said first predetermined thickness.

29. The field effect transistor of claim 28 wherein said first predetermined thickness is sufficiently thick such that said channel substrate is not fully depleted at pinch-off.

30. The field effect transistor of claim 29 wherein said first predetermined thickness is at least ##EQU68## where V_dd is the power supply voltage for said field effect transistor.

31. The field effect transistor of claim 25 wherein said channel comprises a plurality of channels separated from one another by rail regions;

and wherein said gate contact comprises a plurality of gate contacts, a respective one of which overlies a respective one of said plurality of channels.

32. The field effect transistor of claim 25 wherein said thin semiconductor layer comprises a thin layer of monocrystalline silicon.

33. The field effect transistor of claim 25 wherein said channel substrate is doped by an additional dose factor G_i of additional dopant of said second conductivity type at an energy which achieves said predetermined depth A, to thereby provide a depletion mode field effect transistor.

34. The field effect transistor of claim 33 wherein said additional dose factor G_i is controlled to maintain a threshold voltage V, for said depletion mode field effect transistor which is greater than zero, where:

##EQU69## and where T_ox is the thickness of said gate insulating layer and e_i is the dielectric constant of said gate insulating layer.

35. The field effect transistor of claim 33 wherein said additional dose factor G_i has a value of α

.

36. The field effect transistor of claim 33 wherein said additional dose factor G_i has a value equal to two times the length of said channel between said source and drain regions.

37. A field effect transistor comprising:

a thin seimconductor layer having a first surface and a second surface opposite said first surface;

source and drain regions of first conductivity type in said thin semiconductor layer;

a channel substrate of second conductivity type in said thin semiconductor layer at said second surface between said source and drain regions, at least one of the channel substrate thickness and channel substrate doping being selected such that said channel substrate is not fully depleted at pinch-off;

a gate insulating layer on said thin semiconductor layer at said first surface adjacent said channel; and

source, drain and gate contacts for electrically contacting said source and drain regions ad said gate insulating layer respectively.

38. The field effect transistor of claim 37 wherein said thin semiconductor layer, said source, said drain and said channel substrate are all a first predetermined thickness, said first predetermined thickness being greater than ##EQU70## where e_s is the dielectric constant of the thin semiconductor layer, V_dd is the power supply voltage for said field effect transistor, q is equal to 1.6×

10^-19 coulombs and N_a is the dopant density of said channel substrate.

39. The field effect transistor of claim 37 further comprising:

an insulating layer on said thin semiconductor layer at said second surface; and

a substrate on said insulating layer, to thereby produce a semiconductor-on-insulator field effect transistor.