Integrated circuit device having improved substrate capacitance isolation

• US 5,151,775 A
• Filed: 10/07/1991
• Issued: 09/29/1992
• Est. Priority Date: 10/07/1991
• Status: Expired due to Fees

• Current Assignee: Maxim Integrated Products, Inc. (Analog Devices, Inc.)
• Original Assignee: Tektronix Incorporated (Fortive Corp.)
• Inventors: Hadwin, Matthew J.
• Primary Examiner(s): Prenty, Mark V.
• Application Number:
  US07/772,753
• Time in Patent Office: 358 Days
• Field of Search: 357/80, 357/68, 357/51, 357/34
• US Class Current: 257/629
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

An integrated circuit device having improved substrate capacitance isolation for use in a ultra low capacitance probe or an input to an oscilloscope or the like has an electrically conductive layer formed directly underneath an input node on the integrated circuit. The electrically conductive layer has a geometry substantially equal to the input node and is driven by a voltage output from a high impedance unity gain circuit. In one embodiment, the electrically conductive layer is formed in the first metal layer of the integrated circuit while an alternate embodiment an emitter region of a semiconductor device in the high impedance circuit is used as the electrically conductive layer.

Claims

1. An integrated circuit having improved substrate capacitance isolation wherein the integrated circuit has a substrate with a metal layer formed on one surface thereof and a high impedance circuit with an input node formed on an opposite surface with the input node coupling an electrical signal to the high impedance circuit, the improvement comprising an electrically conductive layer having a geometry substantially equal to the input node and being disposed between the input node and the metal layer on the substrate with the electrically conductive layer being immediately underneath and insulated from the input node by an insulating layer with the electrically conductive layer being driven by the output of the high impedance circuit.

2. The integrated circuit as recited in claim 1 wherein the input node comprises a bond pad and a trace run.

3. The integrated circuit as recited in claim 1 wherein the electrically conductive layer is a metal layer.

4. An integrated circuit having improved substrate capacitance isolation wherein the integrated circuit has a substrate with a metal layer formed on one surface thereof comprising:

a input node formed on the opposite surface of the substrate for receiving an electrical signal;

a high impedance circuit formed on the same surface as the input node for receiving the electrical signal from the input node; and

a electrically conductive layer having a geometry substantially equal to the input node and being disposed between the input node and the metal layer of the substrate with the electrically conductive layer being immediately underneath and insulated from the input node by an insulating layer with the electrically conductive layer being driven by the output of the high impedance circuit.

5. The integrated circuit as recited in claim 4 wherein the input node comprises a bond pad and a trace run.

6. The integrated circuit as recited in claim 4 wherein the electrically conductive layer is a metal layer.

7. A method of isolating substrate capacitance in an integrated circuit having a substrate with a metal layer formed on one surface thereof that is at an A. C. ground potential and a high impedance circuit formed on the opposite surface, the steps comprising:

applying an electrical signal to an input node of the high impedance circuit; and

coupling the electrical signal output from the high impedance circuit to an electrically conductive layer having a geometry substantially equal to the input node and being disposed between the input node and the metal layer of the substrate with the electrically conductive layer immediately underneath and insulated from the input node by an insulating layer.