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Integrated circuit device having improved substrate capacitance isolation

  • US 5,151,775 A
  • Filed: 10/07/1991
  • Issued: 09/29/1992
  • Est. Priority Date: 10/07/1991
  • Status: Expired due to Fees
First Claim
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1. An integrated circuit having improved substrate capacitance isolation wherein the integrated circuit has a substrate with a metal layer formed on one surface thereof and a high impedance circuit with an input node formed on an opposite surface with the input node coupling an electrical signal to the high impedance circuit, the improvement comprising an electrically conductive layer having a geometry substantially equal to the input node and being disposed between the input node and the metal layer on the substrate with the electrically conductive layer being immediately underneath and insulated from the input node by an insulating layer with the electrically conductive layer being driven by the output of the high impedance circuit.

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