Programmable universal signaling circuit for a telephone network

• US 5,151,935 A
• Filed: 11/02/1990
• Issued: 09/29/1992
• Est. Priority Date: 12/20/1989
• Status: Expired due to Fees

• Current Assignee: Advent IP LLC
• Original Assignee: XEL Communications, Inc. (ExeLED Holdings, Inc.)
• Inventors: Farrell, David, Slife, Jimmy D.
• Primary Examiner(s): BROWN, THOMAS
• Application Number:
  US07/609,083
• Time in Patent Office: 697 Days
• Field of Search: 379/229, 379/230, 379/234, 379/235, 379/240, 379/201, 379/269, 370/62, 370/56, 370/58.3, 370/58.2, 370/110.1
• US Class Current: 379/240
• CPC Class Codes: H04J 3/12 Arrangements providing for calling or supervisory signals
• CPC Class Codes: H04M 3/005 Interface circuits for subscriber lines current supply H04M19/00 and subgroups; supervisory, monitoring or testing arrangements H04M3/22 and subgroups; in key telephone systems H04M9/006
• CPC Class Codes: H04M 7/0096 Trunk circuits
• CPC Class Codes: H04Q 1/30 Signalling arrangements; Manipulation of signalling currents multiplex systems providing for calling or supervisory signals H04J1/14, H04J3/12
• CPC Class Codes: H04Q 11/04 for time-division multiplexing H04Q11/0001 takes precedence

Abstract

A programmable universal signaling circuit for use in a universal channeling unit of a telephone network. The programmable universal signaling circuit uses a line converter and decoder circuit which under control of a microprocessor generates a unique set of configuration signals for configuring the universal signaling circuit into one of a plurality of standard signaling telephone circuits. The universal signaling circuit can be reconfigured either at the location of the universal channel unit or remotely.

Claims

1. A programmable universal signaling circuit (180) for use in a universal channel unit (40) of a telephone network;

said universal channel unit having;

A, B, E, M SB, and SG telephone network signaling paths, a microprocessor (190) and a PCM interface (170);

said PCM interface being connected to a PCM bus (50), said programmable universal signaling circuit comprising;

means (200) connected to said microprocessor and receptive of data from said microprocessor for generating a unique set of configuration signals corresponding to said received data, said generating means further generating a plurality of different sets of configuration signals corresponding to a plurality of different data received from said microprocessor,

first means (210) connected to said generating means, to said microprocessor, and to said A and B signaling paths for selectively configuring to function as a preselected one of a number of loop circuits, said first generating means being receptive of a first portion of said unique set of configuration signals to configure into said preselected one of said number of loop circuits so as to provide A and B signals over said A and B signaling paths necessary for said preselected one loop circuit, said first configuring means delivering the sensed loop current value or loop voltage value for said A and B signaling paths to said microprocessor, and

second means (220) connected to said generating means, to said microprocessor, and to said E, M, SG, and SB signaling paths for selectively configuring to function as a preselected one of a number of E &

M circuits, said second configuring means being receptive of a second portion of said unique set of configuration signals to configure into said preselected one of said number of E &

M circuits so as to provide E, M, SB, and SG signals over said E, M, SB and SG signaling paths necessary for said selected one E &

M circuit, said second configuring means further delivering the sensed E &

M current value or E &

M voltage value for said E &

M signaling paths to said microprocessor.

2. The programmable universal signaling circuit of claim 1 wherein said generating means comprises:

a line converter (202) connected to said microprocessor to receive said data from said microprocessor,

a decoder (204) connected to the outputs of said line converter for decoding a predetermined number of said outputs of said line converter, and

said unique set of configuration signals being generated from the outputs of said decoder.

3. The programmable universal signaling circuit of claim 1 wherein said first configuring means comprises:

means (320) connected to said generating means, to said microprocessor and to said A and B signaling paths for sensing said loop current or loop voltage for said A and B signaling paths, said sensing means being selectively activated by said first portion of said unique set of configuration signals from said generating means to deliver said sensed loop current value or loop voltage value to said microprocessor.

4. The programmable universal signaling circuit of claim 1 wherein said first configuring means comprises:

a battery feed circuit (333),

a plurality of switches, each of said switches being selectively activated by said first portion of said unique set of configuration signals from said generating means, said plurality of switches at least comprising;

(a) an A ground switch (322) for selectively connecting said A signaling path to ground,

(b) an A battery switch (326) for selectively connecting said A signaling path to said battery feed circuit,

(c) a B ground switch (325) for selectively connecting said B signaling path to ground,

(d) a B battery switch (334) for selectively connecting said B signaling path to said battery feed circuit,

(e) a loop switch (323) for selectively connecting said A and B signaling paths together,

(f) a B ringing switch (329) for selectively connecting ringing to the B signaling path,

(g) a 20 volt DX source, and

(h) a B 20 volt switch for selectively connecting said 20 volt DX source to said B signaling path.

5. The programmable universal signaling circuit of claim 1 wherein said second configuring means comprises:

means (308) connected to said microprocessor and to said E signaling path for sensing current in said E signaling path, said E current sensing means delivering the value of the said sensed E current to said microprocessor, and

means (318) connected to said microprocessor and to said M signaling path for sensing current in said M signaling path, said M current sensing means delivering the value of said sensed M current to said microprocessor.

6. The programmable universal signaling circuit of claim 1 wherein said second configuring means comprises:

a minus 48 volt battery (314),

a plurality of switches, each of said switches being collectively activated by said second portion of said unique set of configuration signals from said generating means, said plurality of switches at least comprising;

(a) an E battery switch (309) for selectively connecting said minus 48 volt battery to said E signaling path,

(b) an M battery switch (317) for selectively connecting said minus 48 volt battery to said M signaling path,

(c) an SB battery switch (310) for selectively connecting said minus 48 volt battery to said SB signaling path,

(d) an E to SG switch (306) for selectively connecting said E signaling path to said SG signaling path,

(e) an SG ground switch (307) for selectively connecting ground to said SG signaling path,

(f) an E ground switch (306) for selectively connecting ground to said E signaling path,

(g) an SB ground switch (319) for selectively connecting ground to said SB signaling path,

(h) an M to SB switch (311) for selectively connecting said M signaling path to said SB signaling path,

(i) an M to SG switch (312) for selectively connecting said M signaling path to said SG signaling path,

(j) an M ground switch (313) for selectively connecting ground to said M signaling path, and

(k) an M detector switch (315) for selectively connecting said M signaling path to either ground or said minus 48 volt battery directly or through a predetermined resistance.

7. The programmable universal signaling circuit of claim 1 wherein said second configuring means comprises an A to SG switch (304) for selectively connecting said SG signaling path to said A signaling path in response to said second portion of said unique set of configuration signals from said generating means for operation in a tandem mode.

8. A programmable universal signaling circuit (180) for use in a universal channel unit (40) of a telephone network;

said universal channel unit having;

A, B, E, M, SB, and SG telephone network signaling paths, a microprocessor (190) and a PCM interface (170);

said PCM interface being connected to a PCM bus (50), said programmable universal signaling circuit comprising;

means (200) connected to said microprocessor and receptive of data from said microprocessor for generating a unique set of configuration signals corresponding to said received data, said generating means further generating a plurality of different sets of configuration signals corresponding to a plurality of different data received from said microprocessor, said generating means comprising;

(i) a line converter (202) connected to said microprocessor to receive said data from said microprocessor,

(ii) a decoder (204) connected to the outputs of said line converter for decoding a predetermined number of said outputs of said line converter, and

(iii) a plurality of different sets of configuration signals corresponding to a plurality of different data received from said microprocessor, said unique set of configuration signals being generated from the outputs of said decoder,

first means (210) connected to said line converter and said decoder, to said microprocessor, and to said A and B signaling paths for selectively configuring to function as a preselected one of a number of loop circuits, said first configuring means being receptive of a first portion of said unique set of configuration signals to configure into said preselected one of said number of loop circuits so as to provide A and B signals over said A and B signaling paths necessary for said preselected one loop circuit, said first configuring means delivering the sensed loop current value or loop voltage value for said A and B signaling paths to said microprocessor, said first configuring means comprising;

(i) a battery feed circuit (333),

(ii) a plurality of switches, each of said switches being selectively activated by said first portion of said unique set of configuration signals, said plurality of switches at least comprising;

(a) an A ground switch (322) for selectively connecting said A signaling path to ground,

(b) an A battery switch (326) for selectively connecting said A signaling path to said battery feed circuit,

(c) a B ground switch (325) for selectively connecting said B signaling path to ground,

(d) a B battery switch (334) for selectively connecting said B signaling path to said battery feed circuit,

(e) a loop switch (323) for selectively connecting said A and B signaling paths together,

(f) a B ringing switch (329) for selectively connecting ringing to the B signaling path,

(g) a 20 volt DX source, and

(h) a B 20 volt switch for selectively connecting said 20 volt DX source to said B signaling path, and

second means (220) connected to said line converter and said decoder, to said microprocessor, and to said E, M, SG, and SB signaling paths for selectively configuring to function as a preselected one of a number of E &

M circuits, said second configuring means being receptive of a second portion of said unique set of configuration signals to configure into said preselected one of said number of E &

M circuits so as to provide E, M, SB, and SG signals over said E, M, SB and SG signaling paths necessary for said selected one E &

M circuit, said second configuring means delivering the sensed E &

M current value or E &

M voltage value for said E &

M signaling paths to said microprocessor, said second configuring means comprising;

(i) a minus 48 volt battery (314),

(ii) a plurality of switches, each of said switches being collectively activated by said second portion of said unique set of configuration signals from said generating means, said plurality of switches at least comprising;

(a) an E battery switch (309) for selectively connecting said minus 48 volt battery to said E signaling path,

(b) an M battery switch (317) for selectively connecting said minus 48 volt battery to said M signaling path,

(c) an SB battery switch (310) for selectively connecting said minus 48 volt battery to said SB signaling path,

(d) an E to SG switch (306) for selectively connecting said E signaling path to said SG signaling path,

(e) an SG ground switch (307) for selectively connecting ground to said SG signaling path,

(f) an E ground switch (308) for selectively connecting ground to said E signaling path,

(g) an SB ground switch (319) for selectively connecting ground to said SB signaling path,

(h) an M to SB switch (311) for selectively connecting said M signaling path to said SB signaling path,

(i) an M to SG switch (312) for selectively connecting said M signaling path to said SG signaling path,

(j) an M ground switch (313) for selectively connecting ground to said M signaling path, and

(k) an M detector switch (315) for selectively connecting said M signaling path to either ground or said minus 48 volt battery directly or through a predetermined resistance.

9. The programmable universal signaling circuit of claim 8 wherein said second configuring means also comprises an A to SG switch (304) for selectively connecting said SG signaling path to said A signaling path in response to said second portion of said unique set of configuration signals for operation in a tandem mode.

10. The programmable universal signaling circuit of claim 8 wherein said first configuring means comprises:

means (320) connected to said line converter and said decoder, to said microprocessor and to said A and B signaling paths for sensing said loop current or loop voltage for said A and B signaling paths, said sensing means being selectively activated by said first portion of said unique set of configuration signals to deliver said sensed loop current value or loop voltage value to said microprocessor.

11. The programmable universal signaling circuit of claim 8 wherein said second configuring means comprises:

means (308) connected to said microprocessor and to said E signaling path for sensing current in said E signaling path, said E current sensing means delivering the value of said sensed E current to said microprocessor, and

means (318) connected to said microprocessor and to said M signaling path for sensing current in said M signaling path, said M current sensing means delivering the value of said sensed M current to said microprocessor.