Clock test apparatus for electronic device

• US 5,153,599 A
• Filed: 06/10/1991
• Issued: 10/06/1992
• Est. Priority Date: 06/11/1990
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Oka, Masaru, Harigae, Masatoshi
• Primary Examiner(s): Issing, Gregory C.
• Application Number:
  US07/712,411
• Time in Patent Office: 484 Days
• Field of Search: 342/352, 342/357, 342/358, 342/165, 342/173, 342/174, 368/202, 331/44, 331/172, 375/111, 455/226, 455/255, 455/316, 324/78 R, 324/78 D, 324/79 R
• US Class Current: 342/352
• CPC Class Codes: G01S 19/235 Calibration of receiver components

Abstract

A clock test apparatus connected to a GPS receiver mounted in a moving body has a frequency counter which counts clocks output from a clock generator incorporated in the GPS receiver for a predetermined period of time. In this manner, a clock frequency is detected and supplied to a clock error identification section. The clock error identification section calculates a short-term stability from the clock frequency, and further calculates a clock error on the basis of the short-term stability. The clock error data is supplied to a dynamics simulator. The dynamics simulator simulates circuit dynamics of the GPS receiver, and models error in the velocity of the moving body relative to a satellite, which results from the clock error, on the basis of the clock error data, thereby analyzing the performance of the GPS receiver.

Claims

1. A clock test apparatus for modeling a clock error of an electronic apparatus including a clock generator, comprising:

a frequency detecting section for detecting the frequency of a clock output from said clock generator; and

a clock error identification section for statistically calculating a short-term stability from an average value of the clock frequency detected by said frequency detecting section, and calculating a clock error on the basis of the short-term stability;

wherein said clock error identification section executes;

a first step of statistically calculating a short-term stability on the basis of a time-based average of the clock frequency detected by said frequency detecting section;

a second step of subjecting the clock error to polynomial-approximation by using formulas representing short-term stability of error sources which result in the clock error on the basis of the short-term stability obtained in the first step;

a third step of calculating a frequency spectrum density of the error sources on the basis of the coefficients in an approximate formula obtained in the second step;

a fourth step of calculating a power spectrum density which coincides with the frequency spectrum density obtained in the third step, when the power spectrum density is input to a predetermined dynamics representing a transfer function of the error sources;

a fifth step of generating noise in accordance with the power spectrum density obtained in the fourth step;

a sixth step of calculating values of the error sources by inputting the noise generated in the fourth step in the dynamics of the error sources; and

a seventh step of calculating the clock error by adding together the values of the error sources obtained in the sixth step;

said clock test apparatus further comprising a dynamics simulator for simulating circuit dynamics of said electronic apparatus, receiving the clock error obtained by said clock error identification section, and calculating an error in the circuit operation of said electronic apparatus resulting from said clock error.

2. A clock test apparatus according to claim 1, wherein said frequency detecting section includes a frequency counter for counting clocks output from said clock generator over a predetermined period of time.

3. A clock test apparatus according to claim 1, wherein said error sources include frequency random walk, frequency flicker noise, frequency white noise, and phase white noise.

4. A clock test apparatus according to claim 1, wherein:

said electronic apparatus is a GPS receiver which is mounted in a moving body, and detects, by means of a clock, the Doppler frequency of a radio wave received by said GPS receiver, thereby obtaining a relative velocity of the moving body with respect to a satellite on the basis of the detected frequency;

said clock generator generates a clock which is to be used in detecting the Doppler frequency of the received radio wave; and

said dynamics simulator simulates circuit dynamics of said GPS receiver, receives a clock error obtained by said clock error identification section, and calculates an error resulting from the clock error in the circuit operation of said electronic apparatus.

5. A clock test apparatus for modeling a clock error of an electronic apparatus including a clock generator, comprising:

a first arithmetic means for receiving coefficients of formulas representing short-term stability of error sources which results in a clock error in the clock generator, and calculating frequency spectrum densities of the error sources on the basis of the coefficients;

a second arithmetic means for calculating a power spectrum density which coincides with the frequency spectrum density obtained in the first arithmetic means, when the power spectrum density is input to a predetermined dynamics representing a transfer function of the error sources;

a third arithmetic means for generating noise in accordance with the power spectrum density obtained by the second arithmetic means;

a fourth arithmetic means for calculating values of the error sources by substituting the noise generated by the third arithmetic means in the dynamics of the error sources;

a fifth arithmetic means for calculating the clock error by adding the values of the error sources obtained by the fourth arithmetic means; and

a dynamics simulator for simulating circuit dynamics of said electronic apparatus, receiving the clock error obtained by said fifth arithmetic means, and calculating an error in the circuit operation of said electronic apparatus resulting from said clock error.