Universal pad pitch layout
First Claim
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1. A universal pad pitch layout method for incrementally varying pad pitches for a fixed row of pads comprising:
- defining a grid size, wherein the grid size is a base unit of measure for pad widths and pad spacings;
defining a minimum pad width, wherein the pad width is an integer multiple of the grid size;
defining a uniform pad height;
defining a minimum pad pitch, wherein the minimum pad pitch is an integer multiple of the grid size;
forming a row of pads;
defining an incremental pad pitch, wherein predetermined pads in the row of pads can be contacted at a pad pitch equal to the minimum pad pitch plus an integer multiple of the incremental pad pitch;
varying the width of predetermined pads in the row of pads by increments of the grid size;
varying the pad pitch between predetermined pads by increments of the grid size; and
combining variations in the pad width and the pad pitch to create a pad pattern wherein all pads can be contacted at the minimum pad pitch and predetermined pads can be contacted at the minimum pad pitch plus an integer multiple of the incremental pad pitch.
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Abstract
A method for configuring a plurality of pads (305) on a semiconductor die (300) to accommodate more than one pad pitch. Pad sizes and pad to pad spacings are adjusted to achieve the pad configuration. A pattern may form in the pad configuration. The pattern is repeated to meet the number of pads needed in an application. Even though the pad pitch changes to accommodate various sizes of I/O'"'"'s and package lead pitches, a fixed contact pitch probe card can be used for various pad pitches and patterns.
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Citations
19 Claims
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1. A universal pad pitch layout method for incrementally varying pad pitches for a fixed row of pads comprising:
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defining a grid size, wherein the grid size is a base unit of measure for pad widths and pad spacings; defining a minimum pad width, wherein the pad width is an integer multiple of the grid size; defining a uniform pad height; defining a minimum pad pitch, wherein the minimum pad pitch is an integer multiple of the grid size; forming a row of pads; defining an incremental pad pitch, wherein predetermined pads in the row of pads can be contacted at a pad pitch equal to the minimum pad pitch plus an integer multiple of the incremental pad pitch; varying the width of predetermined pads in the row of pads by increments of the grid size; varying the pad pitch between predetermined pads by increments of the grid size; and combining variations in the pad width and the pad pitch to create a pad pattern wherein all pads can be contacted at the minimum pad pitch and predetermined pads can be contacted at the minimum pad pitch plus an integer multiple of the incremental pad pitch. - View Dependent Claims (2, 3, 4)
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5. A method for accommodating variable pad pitches for a fixed row of pads on a semiconductor chip comprising:
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defining a minimum pad size, a minimum pad pitch and an incremental pad pitch; defining a unique placement for each pad in a row of pads; increasing pad areas of predetermined pads in the row of pads at integer multiples of the incremental pad pitch, wherein each pad area and the unique placement allows more than one pad pitch to be accommodated; and providing pads to be used at a predetermined pad pitch, the predetermined pad pitch comprising the minimum pad pitch plus any integer multiple of the incremental pad pitch. - View Dependent Claims (6, 7, 8, 9, 10, 11)
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12. A method for configuring pads on a semiconductor die which allows pad contact at more than one pad pitch comprising:
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defining a sequence of pads having a uniform size and a uniform pad pitch; and adjusting pad areas of predetermined pads in the sequence of pads to change contact areas of pads; forming a unique sequence of pads which can accommodate more than one pad pitch; and fixing the unique sequence of pads in a predetermined area on the semiconductor die. - View Dependent Claims (13, 14, 15, 16)
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17. A method for forming two rows of semiconductor pads which allows semiconductor pad contact at 50, 75, 100, 125, and 150 micron pad pitches comprising:
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defining a semiconductor pad height; defining a semiconductor pad width, wherein a semiconductor pad with is 50 microns wide or 75 microns wide; defining spacings between adjacent pads as a 25 micron wide space or a 50 micron wide space; staggering the two rows of semiconductor pads defining a reference line which aligns the two rows of semiconductor pads to one another; forming a first row of semiconductor pads, starting at the reference line and listing semiconductor pad widths and semiconductor pad spacings in sequential order, the first row of semiconductor pads comprising a 50 micron wide pad, 25 micron space, 75 micron wide pad, 50 micron space, 75 micron wide pad, 25 micron space, 50 micron wide pad, 25 micron space, 75 micron wide pad, 50 micron space, 75 micron wide pad, 25 micron space, 50 micron wide pad, 25 micron space, 75 micron wide pad, 50 micron space, 75 micron wide pad, 25 micron space, 50 micron wide pad, 25 micron space, 75 micron wide pad, 50 micron space, 75 micron wide pad, 25 micron space, 50 micron wide pad, 25 micron space, 75 micron wide pad, 50 micron space, 75 micron wide pad, and a 25 micron space; and forming a second row of semiconductor pads adjacent to the first row of semiconductor pads, starting at the reference line and listing semiconductor pad widths and semiconductor pad spacings in sequential order, the second row of semiconductor pads comprising a 25 micron space, 75 micron wide pad, 50 micron space, 50 micron wide pad, 50 micron space, 75 micron wide pad, 25 micron space, 50 micron wide pad, 50 micron space, 50 micron wide pad, 50 micron space, 50 micron wide pad, 50 micron space, 50 micron wide pad, 50 micron space, 75 micron wide pad, 25 micron space, 50 micron wide pad, 50 micron space, 50 micron wide pad, 25 micron space, 75 micron wide pad, 50 micron space, 50 micron wide pad, 50 micron space, 50 micron wide pad, 50 micron space, 50 micron wide pad, 50 micron space, and a 50 micron wide pad. - View Dependent Claims (18, 19)
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Specification