Devices and method for generating and using systems, software waitstates on address boundaries in data processing
First Claim
1. A data processing device for use with peripheral devices having addresses and differing communication response periods, the data processing device comprising:
- digital processor means for selecting different ones of the peripheral devices by asserting on a bus addresses of each selected peripheral device;
addressable programmable registers for holding wait state values representative of distinct numbers of wait states corresponding to different address ranges; and
generator means, connected to the addressable programmable registers, responsive to an asserted address to said peripheral devices asserted by said digital processor means for generating a wait signal comprising a number of wait states represented by the value held in one of the addressable programmable registers and communicated to said generator means, said value corresponding to one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.
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Accused Products
Abstract
A data processing device is used with peripheral devices having addresses and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.
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Citations
20 Claims
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1. A data processing device for use with peripheral devices having addresses and differing communication response periods, the data processing device comprising:
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digital processor means for selecting different ones of the peripheral devices by asserting on a bus addresses of each selected peripheral device; addressable programmable registers for holding wait state values representative of distinct numbers of wait states corresponding to different address ranges; and generator means, connected to the addressable programmable registers, responsive to an asserted address to said peripheral devices asserted by said digital processor means for generating a wait signal comprising a number of wait states represented by the value held in one of the addressable programmable registers and communicated to said generator means, said value corresponding to one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A data processing device for use with banks of memory having a memory space divisible by memory pages, the data processing device comprising:
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a digital processor and an address bus and a data bus for connecting the digital processor to the banks of memory; storing means, connected to the digital processor, addressable by said digital processor, said digital processor including means for entering values into said storing means defining respective numbers of wait states corresponding to the memory pages; and wait state generator means connected to the address bus for generating the number of wait states defined by a value in said storing means for a particular memory page when an address is asserted by the digital processor on the particular memory page. - View Dependent Claims (10, 11, 12)
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13. A data processing device, comprising:
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a digital processor; a plurality of peripheral devices coupled to said digital processor, the peripheral devices having addresses addressable by said digital processor, said peripheral devices having different operating speeds for communication with said digital processor; and said digital processor having a higher maximum speed than at least one of said peripheral devices, and said processor including programmable means for generating wait states in response to the asserted addresses of the peripheral devices to accommodate the speed of each slower peripheral device on an individual basis. - View Dependent Claims (14, 15, 16, 17, 18, 19)
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20. A method of operating a data processing device with peripheral devices having addresses and differing communication response periods, the method comprising the steps of:
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programming addressable registers of a data processing device to hold values representative of distinct numbers of wait states corresponding to different address ranges; selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device; and generating a number of wait states, in response to an asserted address to a peripheral device and in response to the value held in one of the programmable registers that corresponds to the address range of the peripheral device, thereby accommodating the data processing device to the differing communication response periods of the peripheral devices.
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Specification