Pipelined apparatus and method for controlled loading of floating point data in a microprocessor

• US 5,155,816 A
• Filed: 08/08/1991
• Issued: 10/13/1992
• Est. Priority Date: 02/10/1989
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kohn, Leslie D.
• Primary Examiner(s): Kriess, Kevin A.
• Application Number:
  US07/742,289
• Time in Patent Office: 432 Days
• Field of Search: 395/375, 395/775, 395/425
• US Class Current: 712/205
• CPC Class Codes: G06F 15/8069 using a cache
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3875 Pipelining a single stage, e.g. superpipelining

Abstract

A microprocessor having a pipelined architecture, an onchip data cache, a floating-point unit, a floating-point data latch and an instruction for accessing infrequently used data from an external memory system is disclosed. The instruction comprises a first-in-first-out memory for accumulating data in a pipeline manner, a first circuit means for coupling data from the external bus to the first-in-first-out memory and a second circuit means for transferring the data stored in the first-in-first-out memory to the floating-point data latch. The second circuit means also couples data from the cache to the first-in-first-out memory in the event of a cache hit. Finally, a bus control means is provided for controlling the orderly flow of data in accordance with the architecture of the microprocessor.

Claims

1. In a microprocessor having a pipelined architecture, a data cache coupled to a floating-point unit along an internal bus, and a bus control unit which controls access to an external memory along an external bus, an apparatus for controlling the pipelined loading of floating-point data in said microprocessor comprising:

a first circuit means for storing floating-point data in a piplined manner as it is received from said external memory;

a bi-directional bus coupling said first circuit means to said internal bus, said bi-directional bus transferring the floating-point data stored in said first circuit means to a floating-point data latch via said internal bus; and

control means for controlling said first circuit means and said data cache so that floating-point data previously stored in said first circuit means may be pipelined to said floating-point data latch without contention of said internal bus by said data cache, and further wherein floating-point data received by said first circuit means is not otherwise written into said data cache.

2. The apparatus of claim 1 wherein said first circuit means comprises an N-stage buffer, where N is an integer greater than 1, coupled to said external bus for delivering data from said external memory to said floating-point unit, but not to said data cache.

3. The apparatus according to claim 2 wherein a separate data address associated with said external memory may be issued for each successive cycle of said external bus thereby providing increased accessing speed to said external memory.

4. The apparatus according to claim 3 wherein floating-point data residing in said cache is returned to said N-stage buffer along said bi-directional bus through a second buffer under the control of said control means whenever a cache hit occurs.

5. The apparatus according to claim 4 wherein said first circuit means comprises:

a first multiplexer having one input coupled to said external bus, another input coupled to said bi-directional bus and an output;

an N-stage first-in-first-out (FIFO) memory having an input and an output, said input being coupled to said output of said first multiplexer;

a second multiplexer having one input coupled to said output of said FIFO memory, another input coupled to said external bus and an output, said output of said second multiplexer being coupled to said bi-directional bus through a third buffer;

said first multiplexer providing data to said FIFO memory either from said external memory in the event of a cache miss or from said data cache in the event of a cache hit; and

said second multiplexer providing data to said bi-directional bus from said FIFO memory, or directly from said external bus.

6. The apparatus according to claim 5 wherein said bi-directional bus is coupled to said internal bus through a fourth buffer, said fourth buffer and said data cache being controlled by said control means such that said data cache is denied access to said internal bus when said bi-directional bus is transferring data to said data latch, thereby avoiding bus contention.

7. The apparatus according to claim 6 wherein each of said buffers comprises a tri-state buffer.

8. In a microprocessor having a pipelined architecture, said microprocessor comprising a data cache coupled to a floating-point data latch along an internal bus, an apparatus for pipelined accessing of floating-point data from an external memory across an external bus comprising;

a memory means for accumulating floating-point data;

a first circuit means for delivering floating-point data from said external memory to said memory means, but not to said data cache, when a cache miss occurs;

a second circuit means for delivering the floating-point data accumulated in said memory means to said data latch, said second circuit means also coupling said data latch to said first circuit means such that floating-point data resident within said data cache is returned to said memory means in the event of a cache hit; and

a bus control means coupled to said first and second circuit means, said memory means, said internal bus and said data cache for controlling the pipelined flow of floating-point data from said external memory to said data latch without contention of said internal bus by said data cache in the event of a cache miss, and for controlling the return of floating-point data from said data cache to said memory means in the event of a cache hit.

9. The apparatus of claim 8 wherein said memory means comprises an N-stage first-in-first-out (FIFO) memory, where N is an integer.

10. The apparatus according to claim 9 wherein said first circuit means comprises a first multiplexer and a first buffer, said first buffer coupling said external bus to one input of said first multiplexer, said first multiplexer having another input coupled to said second circuit means and an output coupled to said FIFO memory.

11. The apparatus according to claim 10 wherein said first buffer also couples said external bus to said second circuit means such that floating point data may be transferred directly to said data latch from said external memory whenever said FIFO memory is empty.

12. The apparatus according to claim 11 wherein said second circuit means comprises a second multiplexer having an output, one input coupled to receive pipelined floating point data from said FIFO memory, and another input coupled to said first buffer,

said second circuit means further comprising a second buffer coupled to said output of said second multiplexer and also to a bi-directional bus for delivering floating-point data to said data latch in the event of a cache miss and returning floating-point data from said data cache to said another input of said first multiplexer in the event of a cache hit.

13. The apparatus according to claim 12 wherein said FIFO memory comprises:

a plurality of registers;

a first selection means for selecting which of said plurality of registers floating-point data is to be written to; and

a second selection means for determining which of said plurality of registers floating-point data is to be read from.

14. The apparatus according to claim 13 wherein said apparatus can issue addresses to said external memory at the full bandwidth of said external bus, and wherein said apparatus returns the Nth previous floating-point data element each clock cycle.

15. In a processor having a pipelined architecture, a data cache coupled to a floating-point unit along an internal bus, and a bus control unit which controls access to an external memory along an external bus, an apparatus for controlling the pipelined loading of floating-point data into said processor comprising:

a first buffer coupled to said external bus for receiving floating-point data from said external memory;

a first circuit means for storing floating-point data in a pipelined manner as it is received from said external memory by said first buffer;

a first bus coupled to said first circuit means and to said internal bus for transferring the floating-point data stored in said first circuit means to a floating-point data latch in the event of a cache miss;

a second bus coupling said data cache to said first circuit means such that floating-point data residing in said cache is returned to said first circuit means when a cache hit occurs; and

a control means for controlling said first buffer, said first circuit means, said first, second and internal buses, and said data cache such that floating-point data received from said external bus is not written directly into said data cache, but wherein floating-point data previously stored in said first circuit means is pipelined to said data latch along said first and internal buses without contention of said internal bus by said data cache when a cache miss occurs, floating-point data being returned to said first circuit means from said data cache along said second bus in the event of a cache hit.

16. The apparatus according to claim 15 wherein said first circuit means comprises:

a first multiplexer having one input coupled to said first buffer, another input coupled to said second bus and an output;

an N-stage first-in-first-out FIFO memory, where N is an integer greater than 1, said FIFO memory having an input coupled to said output of said first multiplexer and an output;

a second multiplexer having one input coupled to said output of said FIFO memory, another input coupled to said first buffer and an output, said output of said second multiplexer being coupled to said first bus through a third buffer;

said first multiplexer providing floating-point data to said FIFO memory either from said external memory in the event of a cache miss or from said data cache in the event of a cache hit; and

said second multiplexer providing floating-point data to said first bus either from said FIFO memory, or directly from said first buffer when said FIFO memory is empty.

19. The apparatus of claim 16 wherein said second multiplexer provides the Nth previously addressed floating-point data element to said first bus.

20. The apparatus of claim 19 wherein said processor may continue to issue new addresses to said external memory while bus cycles on said external bus remain outstanding.

21. The apparatus of claim 20 wherein said processor waits for outstanding bus cycles on said external bus to be completed before returning said floating-point data from said data cache to said FIFO memory in the event of a cache hit.

17. In a processor having a floating-point unit, a data cache and a port to an external memory system, a method for pipelined accessing of floating-point data elements from said external memory, said method being executable by instruction means within said processor, said method comprising the steps of:

(a) issuing an address to a floating-point data element resident within said external memory;

(b) writing a previously addressed floating-point data element from said external memory to a N-stage, first-in-first-out (FIFO) memory, where N is an integer greater than 1, said FIFO memory storing a Nth previously addressed data element;

(c) reading said Nth previously addressed floating-point data element from said FIFO memory to a bus;

(d) transferring said Nth previously addressed floating-point element from said bus to a data latch within said floating-point unit.

18. The method of claim 17 wherein said processor is operable to issue additional addresses to said external memory prior to said writing step.