High performance thin film transistor (TFT) by solid phase epitaxial regrowth

• US 5,156,987 A
• Filed: 12/18/1991
• Issued: 10/20/1992
• Est. Priority Date: 12/18/1991
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Sandhu, Gurtej S., Fazan, Pierre
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US07/812,234
• Time in Patent Office: 307 Days
• Field of Search: 437/40, 437/41, 437/42, 437/44, 437/56, 437/47, 437/52, 437/247, 437/915, 437/233, 437/60, 437/918, 148/DIG. 109
• US Class Current: 438/153
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02502 consisting of two layers
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02598 monocrystalline
• CPC Class Codes: H01L 21/02645 Seed materials
• CPC Class Codes: H01L 21/02667 Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: Y10S 148/109 Memory devices

Abstract

The present invention introduces a method to fabricate an active PMOS thin film transistor (or p-ch TFT) having an epitaxially grown channel region for high performance operation characteristics. Typically this p-ch TFT device would be fabricated overlying an NMOS active device, thereby becoming an active load (or pullup) to an NMOS device used is such applications as creating a memory cell in static random access memories (SRAMs). Conductivity types (p-type or n-type) may be interchanged to construct an n-ch TFT coupled with a PMOS active device if so desired. The fabrication of the TFT of the present invention may be used to form a CMOS inverter or simply an active pullup device when integrated into conventional CMOS fabrication processes.

Claims

1. A process for forming an active load in an integrated circuit fabricated on a single crystalline substrate, said process comprising:

(a) forming a first dielectric layer superjacent existing surface of said single crystalline substrate;

(b) planarizing said first dielectric layer;

(c) forming a first semiconductive layer superjacent said planarized first dielectric layer;

(d) patterning and etching said first semiconductive layer thereby forming a gate terminal to an active device;

(e) forming dielectric spacers adjacent said patterned edges of said first semiconductive layer;

(f) forming a second dielectric layer superjacent and coextensive to wafer surface resulting from step "e";

(g) patterning and etching a buried contact location thereby exposing portions of said single crystalline substrate;

(h) forming a second semiconductive layer superjacent existing wafer surface resulting from step "g", said second semiconductive layer thereby making physical contact to said exposed portions of single crystalline substrate;

(i) patterning and etching said second semiconductive material thereby forming a channel region for said active device and

(j) growing a crystalline structure throughout said patterned second semiconductive material by using said single crystalline substrate as a seed source, said active device serving as said active load.

2. The process of claim 1, wherein said forming of said first semiconductive layer is by deposition and doping of polysilicon.

3. The process of claim 1, wherein said forming of said second dielectric layer is by low pressure chemical vapor deposition of oxide.

4. The process of claim 1, wherein said forming of said second dielectric layer is by low pressure chemical vapor deposition of a combination of oxide and nitride.

5. The process of claim 1, wherein said forming of said second semiconductive layer is by deposition and doping of amorphous polysilicon.

6. The process of claim 5, wherein said doping of said second semiconductive layer is by in-situ doping.

7. The process of claim 5, wherein said doping of said second semiconductive layer is by ion implantation.

8. The process of claim 1, wherein said forming of said crystalline material is by epitaxial regrowth of amorphous silicon throughout said second semiconductive layer by annealing, wherein said single crystalline substrate seed source is a silicon seed source and said second semiconductive layer is amorphous silicon.

9. The process of claim 8, wherein said annealing step comprises heating existing material on said substrate at a temperature range between 500°

to 700°

C. for approximately 15 minutes to 6 hours.

10. A process for forming a p-channel thin film transistor in an integrated circuit fabricated on a single crystalline silicon substrate, said process comprising:

(a) depositing a first oxide layer superjacent existing surface of said single crystalline silicon substrate;

(b) planarizing said first oxide layer;

(c) depositing a first polysilicon layer superjacent said planarized first oxide layer;

(d) patterning and etching said first polysilicon layer thereby forming a gate terminal to said thin film transistor;

(e) depositing and etching oxide spacers adjacent said patterned edges of said first polysilicon layer;

(f) forming a second dielectric layer superjacent and coextensive existing substrate surface resulting from step "e";

(g) patterning and etching a buried contact location thereby exposing portions of said single crystalline silicon substrate;

(h) depositing a layer of amorphous silicon superjacent existing substrate surface resulting from step "g", said amorphous silicon layer thereby making physical contact to said exposed portions of single crystalline silicon substrate;

(i) patterning and etching said amorphous silicon layer thereby forming a channel region for said thin film transistor; and

(j) growing epitaxial silicon throughout said patterned amorphous silicon by using said single crystalline silicon substrate as a seed source by annealing existing material on said substrate at a temperature range between 500°

to 700°

C. for approximately 15 minutes to 6 hours.