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Complementary, isolated DMOS IC technology

  • US 5,156,989 A
  • Filed: 11/08/1988
  • Issued: 10/20/1992
  • Est. Priority Date: 11/08/1988
  • Status: Expired due to Term
First Claim
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1. A method of producing a complementary MOS transistor pair comprising the steps of:

  • providing a lightly doped semiconductor substrate of a first electrical conductivity type having a top surface;

    providing a covering layer of lightly doped semiconductor material of first conductivity type, contiguous to and overlying the top surface of the substrate, with the substrate and the covering layer having an interface therebetween and the covering layer having a top surface;

    providing a slowly diffusing dopant of a second electrical conductivity type opposite to that of the first conductivity type at a first portion of the substrate-covering layer interface, and allowing the slowly diffusing dopant to diffuse into the covering layer to produce a first dopant profile therein;

    providing a rapidly diffusing dopant of second conductivity type at a second portion of the substrate-covering layer interface that is substantially annular and adjoins and laterally surrounds the first portion of the substrate-covering layer interface, and allowing the rapidly diffusing dopant to diffuse upward into the covering layer to produce a second dopant profile therein;

    providing a rapidly diffusing dopant of second conductivity type at a first portion of the top surface of the covering layer that is substantially annular and substantially overlies the second portion of the substrate-first covering layer interface, and allowing this dopant to diffuse downward into the covering layer to produce a third dopant profile that has a top surface and that meets and merges with the second dopant profile, where the first dopant profile, the second dopant profile, the third dopant profile and the top surface of the covering layer bound and define an enclosed region of the covering layer that has a top surface and that is electrically isolated from the substrate and from the remainder of the covering layer;

    providing a rapidly diffusing dopant of second conductivity type at a second portion of said top surface of said covering layer that is spaced apart from and is not laterally surrounded by said first portion of said top surface of said covering layer, and allowing this dopant to diffuse downward into said covering layer to form a fourth dopant profile therein that has a top surface;

    providing two deep fifth dopant profiles of heavily doped first conductivity type extending downward from said top surface of said covering layer and not within said enclosed region, with the first of the fifth dopant profiles lying between and being spaced apart from said third dopant profile and said fourth dopant profile, and with the second of the fifth dopant profiles being spaced apart from said fourth dopant profile and being positioned so that said fourth dopant profile lies between the first and second of the fifth dopant profiles;

    providing three field oxide regions at said top surface of said covering layer, with the first field oxide region being substantially annular in shape and overlying and extending downward into a portion of said third dopant profile and downward into a portion of the first of the fifth dopant profiles, with the second field oxide region being substantially annular in shape and overlying and extending downward into a portion of the enclosed region, and with the third field oxide region overlying and extending downward into a portion of the second of the sixth dopant profiles;

    providing a thin oxide layer of thickness substantially 0.02-0.25 μ

    m over the upper surface of the structure;

    providing three gate regions of doped semiconductor material on the first oxide layer, with the first gate region being substantially annular in shape and laterally surrounding and adjacent to a portion of the second field oxide region, with the second gate region lying above a portion of said covering layer that is spaced apart from and lies between said fourth dopant profile and the first of the fifth dopant profiles, and with the third gate region overlying a portion of said covering layer that is spaced apart from and lies between said fourth dopant profile and the second of the fifth dopant profiles, with each gate region containing polysilicon that is doped to a resistivity of substantially 25-50 Ohm/square;

    providing a thin sixth dopant profile of lightly doped second conductivity type in said covering layer adjacent to said top surface thereof at all portions of said top surface that do not underlie the first, second or third field oxide regions or the first, second or third gate regions;

    providing two seventh dopant profiles of lightly doped first conductivity type in said covering layer adjacent to said top surface thereof, where the first of the seventh dopant profiles lies between the first field oxide region and a portion of said covering layer that underlies the second gate region, and where the second of the seventh dopant profiles lies between the third field oxide region and a portion of said covering layer that underlies the third gate region;

    providing an eighth dopant profile of lightly doped second conductivity type within said enclosed region and adjacent to the top surface thereof where the eighth dopant profile is substantially annular and adjacent to and electrically connected to said third dopant profile and a portion of the eighth dopant profile underlies at least a portion of the first gate region;

    providing four ninth dopant profiles of heavily doped first conductivity type lying in said covering layer or said enclosed region adjacent to said top surface of said covering layer, with the first of the ninth dopant profiles lying in an upper portion of the first of the eighth dopant profiles at a position spaced apart from said third dopant profile, and with a portion of the first of the ninth dopant profiles underlying at least a portion of the first gate region, with the second of the ninth dopant profiles being contiguous and being laterally surrounded by the second field oxide region, with the third of the ninth dopant profiles lying in an upper portion of the first of the seventh dopant profiles at a position adjacent to the first field oxide region and spaced apart from the portion of said covering layer that underlies the second gate region, and with the fourth of the ninth dopant profiles lying in an upper portion of the second of the seventh dopant profiles adjacent to the third field oxide region and spaced apart from the portion of said covering layer that underlies the third gate region;

    providing four tenth dopant profiles of heavily doped second conductivity type within said covering layer or said enclosed region and adjacent to said top surface of said covering layer, with the first of the tenth dopant profiles lying at an upper portion of said third dopant profile and of said enclosed region that extends from the first field oxide region to the first of the ninth dopant profiles, with the second of the tenth dopant profiles lying in an upper portion of the first of the seventh dopant profiles spaced apart from the first field oxide region; and

    with a portion of the second of the tenth dopant profiles underlying at least a portion of the second gate region, with the third of the tenth dopant profiles lying within said fourth dopant profile and being adjacent to a portion of said top surface thereof, and with the fourth of the tenth dopant profiles lying in an upper portion of the second of the seventh dopant profiles spaced apart from the third field oxide region, and with a portion of the fourth of the tenth dopant profiles underlying at least a portion of the third gate region; and

    providing a thick oxide layer over the upper surface of the structure.

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