Complementary, isolated DMOS IC technology

• US 5,156,989 A
• Filed: 11/08/1988
• Issued: 10/20/1992
• Est. Priority Date: 11/08/1988
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Williams, Richard K., Blanchard, Richard A.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): Nguyen, Tuan
• Application Number:
  US07/268,839
• Time in Patent Office: 1,442 Days
• Field of Search: 437/77, 437/41, 437/31, 437/34, 437/56, 437/57, 437/74, 437/76, 148/DIG. 85
• US Class Current: 438/206
• CPC Class Codes: H01L 21/761 PN junctions
• CPC Class Codes: H01L 21/8238 Complementary field-effect transistors, e.g. CMOS
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: Y10S 148/085 Isolated-integrated

Abstract

A process sequence that produces a plurality of pretransistor structures from which a variety of high voltage, isolated integrated circuits and low voltage integrated circuits are easily fabricated.

Claims

1. A method of producing a complementary MOS transistor pair comprising the steps of:

providing a lightly doped semiconductor substrate of a first electrical conductivity type having a top surface;

providing a covering layer of lightly doped semiconductor material of first conductivity type, contiguous to and overlying the top surface of the substrate, with the substrate and the covering layer having an interface therebetween and the covering layer having a top surface;

providing a slowly diffusing dopant of a second electrical conductivity type opposite to that of the first conductivity type at a first portion of the substrate-covering layer interface, and allowing the slowly diffusing dopant to diffuse into the covering layer to produce a first dopant profile therein;

providing a rapidly diffusing dopant of second conductivity type at a second portion of the substrate-covering layer interface that is substantially annular and adjoins and laterally surrounds the first portion of the substrate-covering layer interface, and allowing the rapidly diffusing dopant to diffuse upward into the covering layer to produce a second dopant profile therein;

providing a rapidly diffusing dopant of second conductivity type at a first portion of the top surface of the covering layer that is substantially annular and substantially overlies the second portion of the substrate-first covering layer interface, and allowing this dopant to diffuse downward into the covering layer to produce a third dopant profile that has a top surface and that meets and merges with the second dopant profile, where the first dopant profile, the second dopant profile, the third dopant profile and the top surface of the covering layer bound and define an enclosed region of the covering layer that has a top surface and that is electrically isolated from the substrate and from the remainder of the covering layer;

providing a rapidly diffusing dopant of second conductivity type at a second portion of said top surface of said covering layer that is spaced apart from and is not laterally surrounded by said first portion of said top surface of said covering layer, and allowing this dopant to diffuse downward into said covering layer to form a fourth dopant profile therein that has a top surface;

providing two deep fifth dopant profiles of heavily doped first conductivity type extending downward from said top surface of said covering layer and not within said enclosed region, with the first of the fifth dopant profiles lying between and being spaced apart from said third dopant profile and said fourth dopant profile, and with the second of the fifth dopant profiles being spaced apart from said fourth dopant profile and being positioned so that said fourth dopant profile lies between the first and second of the fifth dopant profiles;

providing three field oxide regions at said top surface of said covering layer, with the first field oxide region being substantially annular in shape and overlying and extending downward into a portion of said third dopant profile and downward into a portion of the first of the fifth dopant profiles, with the second field oxide region being substantially annular in shape and overlying and extending downward into a portion of the enclosed region, and with the third field oxide region overlying and extending downward into a portion of the second of the sixth dopant profiles;

providing a thin oxide layer of thickness substantially 0.02-0.25 μ

m over the upper surface of the structure;

providing three gate regions of doped semiconductor material on the first oxide layer, with the first gate region being substantially annular in shape and laterally surrounding and adjacent to a portion of the second field oxide region, with the second gate region lying above a portion of said covering layer that is spaced apart from and lies between said fourth dopant profile and the first of the fifth dopant profiles, and with the third gate region overlying a portion of said covering layer that is spaced apart from and lies between said fourth dopant profile and the second of the fifth dopant profiles, with each gate region containing polysilicon that is doped to a resistivity of substantially 25-50 Ohm/square;

providing a thin sixth dopant profile of lightly doped second conductivity type in said covering layer adjacent to said top surface thereof at all portions of said top surface that do not underlie the first, second or third field oxide regions or the first, second or third gate regions;

providing two seventh dopant profiles of lightly doped first conductivity type in said covering layer adjacent to said top surface thereof, where the first of the seventh dopant profiles lies between the first field oxide region and a portion of said covering layer that underlies the second gate region, and where the second of the seventh dopant profiles lies between the third field oxide region and a portion of said covering layer that underlies the third gate region;

providing an eighth dopant profile of lightly doped second conductivity type within said enclosed region and adjacent to the top surface thereof where the eighth dopant profile is substantially annular and adjacent to and electrically connected to said third dopant profile and a portion of the eighth dopant profile underlies at least a portion of the first gate region;

providing four ninth dopant profiles of heavily doped first conductivity type lying in said covering layer or said enclosed region adjacent to said top surface of said covering layer, with the first of the ninth dopant profiles lying in an upper portion of the first of the eighth dopant profiles at a position spaced apart from said third dopant profile, and with a portion of the first of the ninth dopant profiles underlying at least a portion of the first gate region, with the second of the ninth dopant profiles being contiguous and being laterally surrounded by the second field oxide region, with the third of the ninth dopant profiles lying in an upper portion of the first of the seventh dopant profiles at a position adjacent to the first field oxide region and spaced apart from the portion of said covering layer that underlies the second gate region, and with the fourth of the ninth dopant profiles lying in an upper portion of the second of the seventh dopant profiles adjacent to the third field oxide region and spaced apart from the portion of said covering layer that underlies the third gate region;

providing four tenth dopant profiles of heavily doped second conductivity type within said covering layer or said enclosed region and adjacent to said top surface of said covering layer, with the first of the tenth dopant profiles lying at an upper portion of said third dopant profile and of said enclosed region that extends from the first field oxide region to the first of the ninth dopant profiles, with the second of the tenth dopant profiles lying in an upper portion of the first of the seventh dopant profiles spaced apart from the first field oxide region; and

with a portion of the second of the tenth dopant profiles underlying at least a portion of the second gate region, with the third of the tenth dopant profiles lying within said fourth dopant profile and being adjacent to a portion of said top surface thereof, and with the fourth of the tenth dopant profiles lying in an upper portion of the second of the seventh dopant profiles spaced apart from the third field oxide region, and with a portion of the fourth of the tenth dopant profiles underlying at least a portion of the third gate region; and

providing a thick oxide layer over the upper surface of the structure.

2. The method of claim 1, further comprising the steps of:

combining said third field oxide region and a portion of said first field oxide region as part of a third substantially annular field oxide region;

combining said first and said second of said fifth dopant profiles as part of a substantially annular, deep, heavily doped region;

combining said second gate region and said third gate region as part of a second substantially annular gate region;

combining said first and said second of said seventh dopant profiles as part of a substantially annular body region;

combining said third and said fourth of said ninth dopant profiles a part of a substantially annular body contact region;

combining said second and said fourth of said tenth dopant profiles as part of a substantially annular source region; and

combining the portions of said sixth dopant profile that lie between said fourth dopant profile and the second substantially annular gate region as part of a substantially annular drift region.

3. The method according to claim 1, further comprising the steps of:

providing a first electrode that is electrically coupled to said first of said ninth dopant profiles and to said first of said tenth dopant profiles;

providing a second electrode that is electrically coupled to said second of said ninth dopant profiles; and

providing an electrical contact for said first gate region.

4. The method of claim 1, further comprising the steps of:

providing an electrode that is electrically coupled to said third of said tenth dopant profiles;

providing an electrode that is electrically coupled to said third of said ninth dopant profiles and to said second or said fourth of said tenth dopant profiles; and

providing an electrical contact for said second or said third gate region.

5. The method of claim 1, further comprising the steps of:

providing a deep eleventh dopant profile of second conductivity type within said enclosed region and extending to the top surface thereof, where the eleventh dopant profile is substantially annular and is positioned between and spaced apart from said eighth dopant profile and said second of said ninth dopant profiles and is adjacent to the portion of said top surface of said enclosed region that underlies gate region;

providing a twelfth dopant profile, of heavily doped first conductivity type, that is contained within the eleventh dopant profile and extends to a portion of the top surface thereof, where a portion thereof underlies at least a portion of said first gate region;

providing a thirteenth dopant profile, of heavily doped second conductivity type, that is contained within the eleventh dopant profile and extends to a portion of the top surface thereof and that lies between said second field oxide region and the twelfth dopant profile; and

providing an electrode that is electrically coupled to the twelfth and thirteenth dopant profiles.

6. The method of claim 1, wherein the step of providing at least one of said fifth dopant profiles, said sixth dopant profiles, said seventh dopant profiles, said eighth dopant profile, said ninth dopant profiles or said tenth dopant profiles comprises the steps of:

providing an aperture in the upper surface of the structure to expose a portion of said top surface of said covering layer or said top surface of said enclosed region that overlies the position of said dopant profile to be formed;

introducing dopant by predeposition in a thin layer at the exposed portion; and

allowing the dopant to move into said covering layer or said enclosed region by diffusion to form said dopant profile.

7. The method of claim 1, wherein the step of providing at least one of said fifth dopant profiles, said sixth dopant profiles, said seventh dopant profiles, said eighth dopant profile, said ninth dopant profiles or said tenth dopant profiles comprises the steps of:

providing an aperture in the upper surface of the structure to expose a portion of said top surface of said covering layer or said top surface of said enclosed region that overlies the position of said dopant profile to be formed;

introducing dopant at the exposed portion by ion implantation into said covering layer or said enclosed region; and

allowing the dopant to move into said covering layer or said enclosed region by diffusion to form said dopant profile.

8. The method of claim 1, wherein said step of providing at least one of said sixth dopant profiles or said seventh profile or . . . or eleventh dopant pr. comprises the steps of:

providing a layer of photoresist material over the upper surface of the structure;

providing a mask of selected portions of the photoresist layer so that a portion of the photoresist layer that overlies the position of the dopant profile to be formed is removed;

introducing dopant by ion implantation through the portion of the photoresist layer that has been removed into said covering layer or said enclosed region; and

allowing the implanted ions to move into said covering layer or said enclosed region by diffusion to form said dopant profile.

9. The method of claim 1, further comprising the steps of:

providing a first electrode that is electrically coupled to said second of said tenth dopant profiles to said third of said ninth dopant profiles, to said fourth of said tenth dopant profiles and to said fourth of said ninth dopant profiles;

providing a second electrode that is electrically coupled to said third and said tenth dopant profiles; and

providing an electrical contact to said second gate region and to said third gate region.

10. A method for producing a bipolar transistor comprising the steps of:

providing a lightly doped semiconductor substrate of a first electrical conductivity type having a top surface;

providing a covering layer of lightly doped semiconductor material of first conductivity type, contiguous to and overlying the top surface of the substrate, with the substrate and the covering layer having an interface therebetween and the covering layer having a top surface;

providing a slowly diffusing dopant of a second electrical conductivity type opposite to that of the first conductivity type at a first portion of the substrate-covering layer interface, and allowing the slowly diffusing dopant to diffuse into the covering layer to produce a first dopant profile therein;

providing a rapidly diffusing dopant of second conductivity type at a second portion of the substrate-covering layer interface that is substantially annular and adjoins and laterally surrounds the first portion of the substrate-covering layer interface, and allowing the rapidly diffusing dopant to diffuse upward into the covering layer to produce a second dopant profile therein;

providing a rapidly diffusing dopant of second conductivity type at a first portion of the top surface of the covering layer that is substantially annular and substantially overlies the second portion of the substrate-first covering layer interface, and allowing this dopant to diffuse downward into the covering layer to produce a third dopant profile that has a top surface and that meets and merges with the second dopant profile, where the first dopant profile, the second dopant profile, the third dopant profile and the top surface of the covering layer bound and define an enclosed region of the covering layer that has a top surface and that is electrically isolated from the substrate and from the remainder of the covering layer;

providing a collector region, of highly doped first conductivity type, positioned within said enclosed region and contiguous to said top surface of said enclosed region and spaced apart from said third dopant profile;

providing an emitter region, of highly doped first conductivity type, positioned within said enclosed region and contiguous to said top surface thereof, where the collector region is spaced apart from the emitter region and from said third dopant profile;

providing a base contact region, of highly doped second conductivity type, within the enclosed region of the covering layer and positioned contiguous to the top surface thereof where the base contact region laterally surrounds and is adjacent to the emitter region and lies between the collector and emitter regions;

providing a base region of second conductivity type, positioned within said enclosed region and underlying and contiguous to the emitter region and to at least a portion of the base contact region; and

providing first, second, third and fourth electrodes, electrically coupled to the collector region, to the emitter region, to the base contact region and to said third dopant profile, respectively.

11. The method of claim 10, wherein said collector region is provided as an annular region within said enclosed region and said emitter region is laterally surrounded by said collector region.

12. The method of claim 10, further comprising the step of providing a deep, heavily doped region of first conductivity type, spaced apart from said third dopant profile and from said base contact region and positioned within said enclosed region and laterally surrounding and extending below said collector region.

13. A method for producing a bipolar transistor comprising the steps of:

providing a lightly doped semiconductor substrate of a first electrical conductivity type having a top surface;

providing a covering layer of lightly doped semiconductor material of first conductivity type, contiguous to and overlying the top surface of the substrate, with the substrate and the covering layer having an interface therebetween and the covering layer having a top surface;

providing a slowly diffusing dopant of a second electrical conductivity type opposite to that of the first conductivity type at a first portion of the substrate-covering layer interface, and allowing the slowly diffusing dopant to diffuse into the covering layer to produce a first dopant profile therein;

providing a rapidly diffusing dopant of second conductivity type at a second portion of the substrate-covering layer interface that is substantially annular and adjoins and laterally surrounds the first portion of the substrate-covering layer interface, and allowing the rapidly diffusing dopant to diffuse upward into the covering layer to produce a second dopant profile therein;

providing a rapidly diffusing dopant of second conductivity type at a first portion of the top surface of the covering layer that is substantially annular and substantially overlies the second portion of the substrate-first covering layer interface, and allowing this dopant to diffuse downward into the covering layer to produce a third dopant profile that has a top surface and that meets and merges with the second dopant profile, where the first dopant profile, the second dopant profile, the third dopant profile and the top surface of the covering layer bound and define an enclosed region of the covering layer that has a top surface and that is electrically isolated from the substrate and from the remainder of the covering layer;

converting the portion of said covering layer material that forms said enclosed region from first conductivity type to second conductivity type;

providing an emitter region of highly doped second conductivity type, positioned within said enclosed region and contiguous to said top surface of said enclosed region and spaced apart from said third dopant profile;

providing a base contact region of highly doped first conductivity type, positioned within said enclosed region and contiguous to said top surface thereof and adjacent to and laterally surrounding the emitter region, spaced apart from said third dopant profile;

providing a base region of first conductivity type, positioned within said enclosed region underlying and contiguous to the emitter region and to at least a portion of the base contact region; and

providing first, second and third electrodes, electrically coupled to the emitter region, to the base contact region and to said third dopant profile, respectively.

14. The method of claim 13, further comprising the step of providing a heavily doped region of second conductivity type as a contact region or said third electrode, the heavily doped region being positioned within said third dopant profile and contiguous to said top surface thereof.

15. A method for producing a parasitic-free MOS transistor comprising the steps of:

providing a lightly doped semiconductor substrate of a first electrical conductivity type having a top surface;

providing a covering layer of lightly doped semiconductor material of first conductivity type, contiguous to and overlying the top surface of the substrate, with the substrate and the covering layer having an interface therebetween and the covering layer having a top surface;

providing a slowly diffusing dopant of a second electrical conductivity type opposite to that of the first conductivity type at a first portion of the substrate-covering layer interface, and allowing the slowly diffusing dopant to diffuse into the covering layer to produce a first dopant profile therein;

providing a rapidly diffusing dopant of second conductivity type at a second portion of the substrate-covering layer interface that is substantially annular and adjoins and laterally surrounds the first portion of the substrate-covering layer interface, and allowing the rapidly diffusing dopant to diffuse upward into the covering layer to produce a second dopant profile therein;

providing a rapidly diffusing dopant of second conductivity type at a first portion of the top surface of the covering layer that is substantially annular and substantially overlies the second portion of the substrate-first covering layer interface, and allowing this dopant to diffuse downward into the covering layer to produce a third dopant profile that has a top surface and that meets and merges with the second dopant profile, where the first dopant profile, the second dopant profile, the third dopant profile and the top surface of the covering layer bound and define an enclosed region of the covering layer that has a top surface and that is electrically isolated from the substrate and from the remainder of the covering layer;

providing a body region of second conductivity type, positioned within said enclosed region and adjacent to said top surface thereof and adjacent to the third dopant profile so that the body region forms a substantially annular region within said enclosed region;

providing a source region of heavily doped first conductivity type, positioned within the body region and contiguous to said top surface of said enclosed region so that the source region forms a substantially annular region within said enclosed region;

providing a drain region of heavily doped first conductivity type, positioned within said enclosed region at the top surface thereof and spaced apart from the body region;

providing an oxide layer that overlies said top surface of said enclosed region;

providing a gate region that is contained within the oxide layer that is substantially annular, that overlies and is spaced apart from a portion of said enclosed region that is adjacent to the source region and that overlies a portion of the source region, and that extends toward the drain region;

providing a ground region of heavily doped first conductivity type within said covering layer and contiguous to said top surface thereof and spaced apart from said enclosed region and from said third dopant profile, to provide a ground reference for the structure;

providing a first electrode that is electrically coupled to the body region, to the source region and to said third dopant profile; and

providing second, third and fourth electrodes that are electrically coupled to the drain region, the gate region and the ground region, respectively.

16. The method of claim 15, further comprising the step of providing a contact region of heavily doped second conductivity type, positioned within said third dopant profile at said top surface thereof and electrically coupled to said first electrode.

17. A method for providing MOS transistors in an electrically isolated twin tub comprising the steps of:

providing a lightly doped semiconductor substrate of a first electrical conductivity type having a top surface;

providing a covering layer of lightly doped semiconductor material of first conductivity type, contiguous to and overlying the top surface of the substrate, with the substrate and the covering layer having an interface therebetween and the covering layer having a top surface;

providing a slowly diffusing dopant of a second electrical conductivity type opposite to that of the first conductivity type at a first portion of the substrate-covering layer interface, and allowing the slowly diffusing dopant to diffuse into the covering layer to produce a first dopant profile therein;

providing a rapidly diffusing dopant of second conductivity type at a second portion of the substrate-covering layer interface that is substantially annular and adjoins and laterally surrounds the first portion of the substrate-covering layer interface, and allowing the rapidly diffusing dopant to diffuse upward into the covering layer to produce a second dopant profile therein;

providing a rapidly diffusing dopant of second conductivity type at a first portion of the top surface of the covering layer that is substantially annular and substantially overlies the second portion of the substrate-first covering layer interface, and allowing this dopant to diffuse downward into the covering layer to produce a third dopant profile that has a top surface and that meets and merges with the second dopant profile, where the first dopant profile, the second dopant profile, the third dopant profile and the top surface of the covering layer bound and define an enclosed region of the covering layer that has a top surface and that is electrically isolated from the substrate and from the remainder of the covering layer;

converting a portion, substantially 20-80 percent, of said covering layer material that forms said enclosed region from first conductivity type to second conductivity type, to form a semiconductor well of first conductivity type and a semiconductor well of second conductivity type within said enclosed region, with each well being bounded by the top surface of said enclosed region;

diffusing a dopant of first conductivity type substantially throughout the portion of said enclosed region that is not converted to second conductivity type;

providing an oxide layer overlying said top surface of said enclosed region;

providing first and second heavily doped regions of first conductivity type in said semiconductor well of second conductivity type and contiguous to said top surface thereof and spaced apart from one another;

providing first and second heavily doped regions of second conductivity type in said semiconductor well of first conductivity type and contiguous to said top surface thereof and spaced apart from one another;

providing a first gate region of doped semiconductor material contained in the oxide layer and spaced apart from said top surface of said enclosed region and overlying a portion of each of the first and second heavily doped regions of first conductivity type;

providing a second gate region of doped semiconductor material contained in the oxide layer and spaced apart form said top surface of said enclosed region and overlying a portion of each of the first and second heavily doped regions of second conductivity type;

providing first and second electrodes that are electrically coupled to the first and second heavily doped regions, respectively;

providing third and fourth electrodes that are electrically coupled to the first and second heavily doped regions of second conductivity type, respectively;

providing a fifth electrode that is electrically coupled to said third dopant profile;

providing a sixth electrode that is electrically coupled to the semiconductor well of first conductivity type; and

providing first and second electrical contacts that are coupled to the first and second gate regions, respectively.

18. The method of claim 17, further comprising the step of providing a third heavily doped region of first conductivity type, positioned in said semiconductor well of first conductivity type and contiguous to said top surface thereof, which is electrically coupled to said sixth electrode.

19. The method of claim 17, further comprising the steps of:

providing a first threshold adjustment region that is doped with dopant of first conductivity type, positioned in said semiconductor well of second conductivity type and adjacent to said top surface thereof and underlying said first gate region; and

providing a second threshold adjustment region that is doped with dopant of second conductivity type, positioned in said semiconductor well of first conductivity type and adjacent to said top surface thereof and underlying said second gate region.

20. A method of producing a high voltage MOS transistor in wraparound isolation comprising the steps of:

providing a lightly doped semiconductor substrate of a first electrical conductivity type having a top surface;

providing a covering layer of lightly doped semiconductor material of first conductivity type contiguous and overlying the top surface of the substrate, with the substrate and the covering layer having an interface therebetween and the covering layer having a top surface;

providing a slowly diffusing dopant of second electrical conductivity type opposite to that of the first conductivity type at a first portion of the substrate-covering layer interface, and allowing the slowly diffusing dopant to diffuse into the covering layer to produce a first dopant profile therein;

providing a rapidly diffusing dopant of second conductivity type at a second portion of the substrate-covering layer interface that is substantially annular and adjoins and laterally surrounds the first portion of the substrate-covering layer interface, and allowing the rapidly diffusing dopant to diffuse upward into the covering layer to produce a second dopant profile therein;

providing a rapidly diffusing dopant of second conductivity type at a first portion of the top surface of the covering layer that is substantially annular and substantially overlies the second portion of the substrate-first covering layer interface, and allowing this dopant to diffuse downward into the covering layer to produce a third dopant profile that has a top surface and that meets and merges with the second dopant profile, where the first dopant profile, the second dopant profile, the third dopant profile and the top surface of the covering layer bound and define an enclosed region of the covering layer that has a top surface and that is electrically isolated from the substrate and from the remainder of the covering layer;

providing a fourth dopant profile of heavily doped first conductivity type extending downward from said top surface of said covering layer and not within said enclosed region, said fourth dopant profile being spaced apart from said third dopant profile;

providing two field oxide regions at said top surface of said covering layer, the first field oxide region being substantially annular in shape and overlying and extending downward into a portion of said third dopant profile and downward into a portion of said fourth dopant profile, and the second field oxide region being substantially annular in shape and overlying and extending downward into a portion of the enclosed region;

providing a thin oxide layer of thickness substantially 0.02-0.25 μ

m over the upper surface of the structure;

providing a gate region of doped semiconductor material on the thin oxide layer, said gate region being substantially annular in shape and laterally surrounding and adjacent to a portion of the second field oxide region, and said gate region containing polysilicon that is doped to a resistivity of substantially 25-50 Ohm/square;

providing a fifth dopant profile of lightly doped second conductivity type within said enclosed region and adjacent to the top surface thereof where the fifth dopant profile is substantially annular and adjacent to and electrically connected to said third dopant profile and where a portion of the fifth dopant profile underlies at least a portion of the gate region;

providing a sixth dopant profile of heavily doped first conductivity type in said enclosed region adjacent to the top surface of said covering layer, said sixth dopant profile lying in an upper portion of the fifth dopant profile at a position spaced apart from said second field oxide region, and a portion of said sixth dopant profile underlying at least a portion of said gate region;

providing an seventh dopant profile of heavily doped second conductivity type within said enclosed region and adjacent to said top surface of said covering layer, said seventh dopant profile lying at an upper portion of said third dopant profile and of said enclosed region that extends from said first field oxide region to said sixth dopant profile; and

providing a thick oxide layer over the upper surface of the structure.