Fabricating a memory cell with an improved capacitor

• US 5,156,993 A
• Filed: 08/17/1990
• Issued: 10/20/1992
• Est. Priority Date: 08/17/1990
• Status: Expired due to Term

• Current Assignee: Transpacific IP Group Limited
• Original Assignee: Industrial Technology Research Institute
• Inventors: Su, Wen-Doe
• Primary Examiner(s): Thomas, Tom
• Application Number:
  US07/568,945
• Time in Patent Office: 795 Days
• Field of Search: 437/38, 437/47, 437/48, 437/52, 437/60, 437/191, 437/193, 437/195, 437/203, 437/228, 437/233, 437/235, 437/919, 357/23.6, 148/DIG. 50, 156/643
• US Class Current: 438/244
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H10B 12/038 the capacitor being in a trench in the substrate
• CPC Class Codes: H10B 12/377 having a storage electrode extension located over the transistor

Abstract

A process for producing a random access memory cell having an improved capacitor structure that thereby permits greater integration. The capacitor is a merged combination of a stacked trench and a stacked capacitor which has at least two plates separated by a dielectric layer. The plates are formed of polysilicon and extend partially over the gate region, over the source region, over the sidewalls and bottom of a trench, and partially over the field oxide.

Claims

1. A process for producing a dynamic random access memory cell having a merged stacked trench and stacked capacitor comprising the steps of:

(a) selectively forming field oxide areas on the surface of a semiconductor substrate while leaving device areas for fabrication of field effect devices,

(b) forming trenches in said device areas adjacent the edges of said field oxide areas,

(c) forming a first insulating layer on the surface of said trenches,

(d) depositing a first layer of polysilicon on the surface of said substrate, including the sidewalls and bottom of said trench, of a thickness to substantially fill said trench,

(e) removing portions of said first polysilicon layer but leaving portions thereof for the gate structure in said device area, portions over said field oxide, and portions in said trench,

(f) forming source and drain regions in said device areas by masking and ion implantation techniques, utilizing said portions of said first polysilicon layer, for gate structure as a blocking mask,

(g) depositing a second insulating layer of silicon oxide over said substrate and forming openings over as said source regions, and subsequently removing said portions of said first polysilicon layer in said trench.

(h) forming a second doped polysilicon layer over the surface of said substrate including the sidewalls and bottom of said trench and opening over said source region, said second polysilicon layer to serve as a first capacitor plate,

(i) forming a third insulating layer over the surface of said second polysilicon layer,

(j) forming a third doped polysilicon layer over said insulating layer, said third polysilicon layer to serve as a second capacitor plate, said resultant structure forming a memory cell with a coupled capacitor and a field effect transistor.

2. The process of claim 1 wherein a plurality of said field effect transistors and coupled capacitor structures forms a high density, high speed, dynamic random access memory device.

3. The process of claim 1 wherein individual P and N types regions are formed in said substrate, and said plurality of FETs and coupled capacitor structures are each associated with one of said regions to form complimentary metal over silicon devices.

4. The process of claim 1 wherein said trenches formed in said substrate each have a depth of between 1 to 4 micrometers and a width of between 0.6 to 1.0 micrometers, and the thickness of said first polysilicon layer is at least one-half of the width of said trench.

5. The process of claim 4 wherein said source and drain regions have a graded profile, formed by initially ion implanting at a low acceleration voltage, using said portions of said first polysilicon gate layer as a mask, and subsequently forming blocking mask portion of oxide in the vertical surfaces of said polysilicon portions and ion implanting with a higher dosage and a relatively low acceleration voltage.

6. The process of claim 1 wherein said first insulating layer on the surfaces of said trench is formed by exposing the surfaces thereof to an oxidizing environment, said resultant silicon dioxide layer having a thickness of

7. The process of claim 1 which further includes process steps to provide device structure to reduce gated diode leakage at the storage node and additionally comprising:

initially forming a masking layer to mask device surface regions prior to forming said field oxide areas,

forming said field oxide areas by exposing the unmasked are to a highly oxidizing environment,

removing portions of said masking layer,

forming trenches by reactive ion etching through the resultant openings,

forming a first insulating layer on the surfaces of said trenches,

removing further portions of said masking layer over the top edges of the trenches and exposing the interface of the underlying device material and the first insulating layer on the trench surfaces,

thermally oxidizing the resultant exposed device material to an oxidizing environment resulting in forming a fifth insulating layer of thermal oxide over said interface.

8. The process of claim 13 wherein said masking layer is a composite of an underlying layer of silicon dioxide and an overlying layer of silicon nitride.

9. The process of claim 1 wherein said first polysilicon layer has a thickness of between 2000 to 5000 Angstroms.

10. The process of claim 7 wherein said third polysilicon layer has thickness between 1000 to 3000 Angstroms.

11. The process of claim 6 wherein said second polysilicon layer has a thickness of between 1000 to 2000 Angstroms.

12. The process of claim 7 wherein said third insulating layer on said second polysilicon layer is formed by exposing said layer to an oxidizing environment, said insulating layer having a thickness of between 50 to 200 Angstroms.

13. The process of claim 9 wherein fourth insulating blanket layer is formed over said third polysilicon layer, said blanket layer having a thickness in the range of 200 to 1000 Angstroms.

14. The process of claim 11 wherein said fourth insulating blanket layer is of silicon dioxide, formed by using low temperature deposition techniques.

15. The method of claim 1 wherein said field oxide regions are formed by initially masking the substrate with a composite layer of a lower layer of Si0₂ and an overlay layer of Si₃ N₄ over the device areas, oxidizing the substrate to form oxide regions in the unmasked areas, and subsequently removing said composite layer following the forming of said first insulating layer, and forming a gate insulation layer on the surface of said device area.