Variable decimation architecture for a delta-sigma analog-to-digital converter

• US 5,157,395 A
• Filed: 03/04/1991
• Issued: 10/20/1992
• Est. Priority Date: 03/04/1991
• Status: Expired due to Term

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Crystal Semiconductor Corporation (Cirrus Logic Incorporated)
• Inventors: Klaas, Jeffrey M., Del Signore, Bruce, Swanson, Eric J., Medlock, David L.
• Primary Examiner(s): Logan, Sharon D.
• Application Number:
  US07/664,034
• Time in Patent Office: 596 Days
• Field of Search: 341/143, 341/110, 341/126, 341/144, 341/155, 364/724.1, 364/724.13, 364/724.16, 364/724.01
• US Class Current: 341/143
• CPC Class Codes: H03H 17/0294 Variable filters; Programmable filters
• CPC Class Codes: H03H 17/0664 where the output-delivery frequency is lower than the input sampling frequency, i.e. decimation

Abstract

An analog-to-digital converter includes a delta-sigma modulator (10), having the output thereof filtered by a digital filter section. The digital filter section includes a first fixed decimation filter (12) followed by a variable decimation filter section (14) and an output low-pass filter section (16), having a fixed decimation ratio. The fixed variable decimation filter section (14) includes a single FIR filter (24) that has data processed therethrough with different sampling rates. A recursive controller (26) receives an external configuration input to determine the number of passes through the filter (24) that are required to provide the desired decimation ratio.

Claims

1. A digital filter for receiving an input digital signal and outputting a decimated digital signal, comprising:

a first digital filter section having a fixed decimation ratio and for decimating the input digital signal from a first sampling frequency to a second sampling frequency that is lower than said first sampling frequency; and

a second digital filter section having a variable decimation ratio selected in response to receiving a configuration control signal, said second digital filter section operable to receive a digital signal output at said second sampling frequency from said first digital filter section and to output a digital signal at a third sampling frequency that is lower than said second sampling frequency by a ratio corresponding to said variable decimation ratio.

2. The digital filter of claim 1, and further comprising a configuration input for receiving said configuration control signal, said configuration control signal being externally generated.

3. The digital filter of claim 1, wherein said second digital filter section comprises:

a plurality of fixed decimation filter sections, each having a different and fixed decimation ratio; and

a configuration controller for selecting one of said plurality of fixed decimation filter sections for receiving the output of said first digital filter section.

4. The digital filter of claim 1, wherein the input digital signal is a one-bit digital word.

5. The digital filter of claim 4, wherein the input digital signal is generated by a delta-sigma modulator.

6. The digital filter of claim 1, wherein said second digital filter section comprises:

a plurality of fixed decimation filter sections, each having a fixed decimation ratio and an input and an output; and

a configuration controller for selecting one or more of said fixed decimation filter sections, each having an associated transfer function, and cascading said selected fixed decimation filter sections with the input of one of said selected fixed decimation filter sections connected to the output of one of said selected fixed decimation filter sections in said cascade configuration, the output of a last of said selected fixed decimation filter sections providing the output of said second digital filter section.

7. The digital filter of claim 6, wherein the decimation ratio of each of said fixed decimation filter sections is substantially identical.

8. The digital filter section of claim 6, wherein the transfer function of each of said fixed decimation filter sections is substantially similar.

9. The digital filter section of claim 6, wherein each of said fixed decimation filter sections are arranged in a predetermined cascadable order.

10. The digital filter of claim 1, wherein said second digital filter section comprises:

a single fixed decimation filter section having an input and an output, and operating at a fixed decimation ratio and at a plurality of different sampling rates;

a clock generator for generating said plurality of sampling rates; and

a controller for processing data through said fixed decimation filter section for a plurality of passes, said controller controlling said clock generator to generate a clock frequency associated with the sampling rate of said fixed decimation filter section during each pass, said controller outputting data from a last of said plurality of passes through said fixed decimation filter section as the output of said second digital filter section.

11. The digital filter of claim 10, and further comprising an output register for storing the data output from said single fixed decimation filter section for each pass therethrough and for outputting the data stored in said output register as the output of said second digital filter section after the last pass through said fixed decimation filter section.

12. The digital filter of claim 11, wherein said fixed decimation filter section is a Finite Impulse Response filter and said fixed decimation filter section comprises:

a multiplier having first and second inputs for receiving data on one input thereof and for receiving First Impulse Response (FIR) filter coefficients on the second input thereof and for outputting products of said received data and said FIR filter coefficients on said first and second inputs, respectively;

an accumulator for accumulating the products output by said multiplier for each operation of said multiplier during a given pass as accumulated values, the accumulated values stored in said output register;

said multiplier and accumulator operating at the sampling rate output by said clock generator;

a memory for storing said FIR filter coefficients for each pass through said multiplier and accumulator; and

a multiplexer for accessing the data stored in said output register that was generated from a preceding pass, and inputting the accessed data either to the first input of said multiplier for a given pass, or as the output of said second digital filter section after the last of said plurality of passes through said fixed decimation filter section.

13. The digital filter of claim 1, wherein said first digital filter section is a Finite Impulse Response filter and said second digital filter section is a Finite Impulse Response filter.

14. A digital filter for receiving an input digital signal and outputting a decimated digital signal, comprising:

a single fixed decimation filter section having an input and an output and operating at a fixed decimation ratio and operating at a plurality of different sampling rates for receiving input data at one sampling rate and outputting data at a different sampling rate;

a clock generator for generating said plurality of sampling rates; and

a controller for processing data through said fixed decimation filter section for a plurality of passes, said controller controlling said clock generator to generate a clock frequency associated with the sampling rate of said fixed decimation filter section during each pass, said controller outputting data from a last of said plurality of passes through said fixed decimation filter section as the output decimated digital signal of the digital filter.

15. The digital filter of claim 14, and further comprising an output register for storing the data output from said single fixed decimation filter section for each pass therethrough and for outputting the data stored in said output register as the output decimated digital signal of the digital filter after the last pass through said fixed decimation filter section.

16. The digital filter of claim 15, wherein said fixed decimation filter section is a Finite Impulse Response filter and said fixed decimation filter section comprises:

a multiplier having first and second inputs for receiving data on one input thereof and for receiving First Impulse Response (FIR) filter coefficients on the second input thereof and for outputting products of said received data and said FIR filter coefficients on said first and second inputs, respectively;

an accumulator for accumulating the products output by said multiplier for each operation of said multiplier during a given pass as accumulated values, the accumulated values stored in said output register;

said multiplier and accumulator operating at the sampling rate output by said clock generator;

a memory for storing said FIR filter coefficients for each pass through said multiplier and accumulator; and

a multiplexer for accessing the data in said output register that was generated from a preceding pass and inputting the accessed data either to the input of said multiplier for a given pass, or as the decimated digital signal output by the digital filter after the last of said plurality of passes through said fixed decimation filter section.

17. The digital filter section of claim 14, wherein the input digital signal is a one-bit digital word.

18. The digital filter of claim 17, wherein the input digital signal is received from a delta-sigma modulator.

19. An analog-to-digital converter for receiving an input analog signal and converting it to a digital signal, comprising:

an analog modulator having an output and for converting an analog input signal to an n-bit digital word, where n is an integer;

a first digital filter section having a fixed decimation ratio and for decimating the output of said analog modulator from a first sampling frequency to a second sampling frequency that is lower than said first sampling frequency; and

a second digital filter section having a variable decimation ratio selected in response to receiving a configuration control signal, said second digital filter section operable to receive the output of said analog modulator at said second sampling frequency from said first digital filter section and to output a digital signal at a third sampling frequency that is lower than said second sampling frequency by a ratio corresponding to said variable decimation ratio.

20. The digital filter of claim 19, and further comprising, a third digital filter section having a fixed decimation ratio and providing a low pass filter function, said third digital filter section for receiving and filtering the output of said second digital filter section.

21. The analog-to-digital converter of claim 19, wherein said analog modulator comprises a delta-sigma modulator.

22. The analog-to-digital converter of claim 19, and further comprising a configuration input for receiving said configuration control signal, said configuration control signal being externally generated.

23. The analog-to-digital converter of claim 19, wherein said second digital filter section comprises:

a plurality of fixed decimation filter sections, each having a different and fixed decimation ratio; and

a configuration controller for selecting one of said plurality of fixed decimation filters for receiving the output of said first digital filter section.

24. The analog-to-digital converter of claim 19, wherein the value of n is equal to "1", such that a 1-bit digital stream is output by said analog modulator.

25. The analog-to-digital converter of claim 19, wherein said second digital filter section comprises:

a plurality of fixed decimation filter sections, each having a fixed decimation ratio and an input and an output; and

a configuration controller for selecting one or more of said fixed decimation filter sections, each having an associated transfer function, and cascading said selected fixed decimation filter sections, with the input of one of said selected fixed decimation filters connected to the output of said selected fixed decimation filter sections in said cascade configuration, the output of a last of said selected fixed decimation filter sections providing the output of said second digital filter section.

26. The analog-to-digital converter of claim 25, wherein the decimation ratio of each of said fixed decimation filter sections is substantially identical.

27. The analog-to-digital converter of claim 25, wherein the transfer function of each of said fixed decimation filter sections is substantially similar.

28. The analog-to-digital converter of claim 25, wherein said fixed decimation filter sections are arranged in a predetermined cascadable order.

29. The digital filter of claim 19, wherein said second digital filter section comprises:

a single fixed decimation filter section having an input and an output, and operating at a fixed decimation ratio and at a plurality of different sampling rates;

a clock generator for generating said plurality of sampling rates; and

a controller for processing data through said fixed decimation filter section for a plurality of passes, said controller controlling said clock generator to generate a clock frequency associated with the input sampling rate to said fixed decimation filter section during each pass, said controller outputting the data from the last of said plurality of passes through said fixed decimation filter section as the output of said second digital filter section.

30. The digital filter of claim 29, and further comprising an output register for storing output data from said single fixed decimation filter section for each pass therethrough and for outputting the data stored in said output register as the output of said digital filter after the last pass through said fixed decimation filter section.

31. The digital filter of claim 30, wherein said fixed decimation filter section is a Finite Impulse Response filter and said fixed decimation filter section comprises:

a multiplier having first and second inputs for receiving data on one input thereof and for receiving First Impulse Response (FIR) filter coefficients on the second input thereof and for outputting products of said received data and said FIR filter coefficients on said first and second inputs, respectively;

an accumulator for accumulating the products output by said multiplier for each operation of said multiplier during a given pass as accumulated values, the accumulated values stored in said output register;

said multiplier and accumulator operating at the sampling rate output by said clock generator;

a memory for storing said FIR filter coefficients for each pass through said multiplier and accumulator; and

a multiplexer for accessing the data stored in said output register that was generated from a preceding pass, and inputting the accessed data either to the first input of said multiplier for a given pass, or as the output of said second digital filter section after the last of said plurality of passes through said fixed decimation filter section.

32. The digital filter of claim 19, wherein said first digital filter section is a Finite Impulse Response filter and said second digital filter is a Finite Impulse Response filter.

33. A method for digitally filtering an input digital signal to output a decimated digital signal, comprising the steps of:

providing a first digital filter section;

decimating the input digital signal from a first sampling frequency to a second sampling frequency in the first digital filter section, the second sampling frequency being lower than the first sampling frequency;

providing a second digital filter section having a variable decimation ratio;

selecting the variable decimation ratio in response to receiving a configuration control signal; and

receiving the decimated input signal at the second sampling frequency and outputting a digital signal at a third sampling frequency that is lower than the second sampling frequency by a ratio corresponding to the variable decimation ratio of the second digital filter section.

34. The method of claim 33 wherein the step of providing the second digital filter section comprises providing a plurality of fixed decimation filter sections, each having a different and fixed decimation ratio, and wherein the step of selecting the variable decimation ratio comprises selecting one of the plurality of fixed decimation filter sections for receiving the output of the first digital filter section.

35. The method of claim 33 and further comprising generating the input digital signal with a delta-sigma modulator and outputting a one-bit digital word.

36. The method of claim 33 wherein the step of providing the second digital filter section comprises:

providing a plurality of fixed decimation filter sections, each having a fixed decimation ratio and an input and an output; and

selecting one or more of the fixed decimation filter sections, each having an associated transfer function, and cascading the selected fixed decimation filter sections with the input of one of the selected ones of the fixed decimation filter sections connected to the output of one of the selected fixed decimation filter sections in the cascade configuration, the output of a last of the selected fixed decimation filter sections providing the output decimated digital signal.

37. The method of claim 33 wherein the step of providing the second digital filter section comprises providing a single fixed decimation filter section having an input and an output, and operating at a fixed decimation ratio and at a plurality of different sampling rates and wherein the step of selecting the variable decimation ratio comprises:

providing a clock generator for generating a plurality of sampling rates;

processing data through the fixed decimation filter section for a plurality of passes and controlling the clock generator to generate a clock frequency associated with the sampling rate of the fixed decimation filter section during each pass through the fixed decimation filter section, with each successive pass having a lower associated sampling rate; and

outputting data from the last of the passes through the fixed decimation filter section as the output decimated digital data.

38. A method for digitally filtering an input digital signal and outputting a decimated digital signal having associated therewith a decimated sampling frequency, comprising the steps of:

providing a single fixed decimation filter section having an input and an output and operating at a fixed decimation ratio and operating at a plurality of different sampling rates;

providing a clock generator for generating the plurality of sampling rates;

processing data through the fixed decimation filter section for a plurality of passes;

controlling the clock generator to generate a clock frequency associated with the sampling rate of the fixed decimation filter section during each pass; and

outputting data from a last of the passes to the fixed decimation filter section as the output decimated signal at the decimated sampling frequency.