ESD protection circuit with segmented buffer transistor

• US 5,157,573 A
• Filed: 01/31/1991
• Issued: 10/20/1992
• Est. Priority Date: 05/12/1989
• Status: Expired due to Term

• Current Assignee: Western Digital Corporation
• Original Assignee: Western Digital Corporation
• Inventors: Lee, Kowk Fai V., Lee, Alan
• Primary Examiner(s): DEBOER, TODD
• Application Number:
  US07/648,577
• Time in Patent Office: 628 Days
• Field of Search: 361/58, 361/56, 361/91, 361/111, 357/23.13
• US Class Current: 361/56
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H01L 27/0288 using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution

Abstract

An electrostatic discharge protection circuit for an integrated circuit employing a segmented field effect buffer transistor between the input/output pad and the active devices on the integrated cicuit. An extended resistive structure is configured in series with the segmented buffer transistor and the input/output electrical contact pad. The extended resistive structure is integrally formed with the individual segments of the buffer FET. The resistive structure may be implemented as an extended n well structure adjacent the FET segments. In a first resistance mode during normal circuit operations, the extended resistive structure has a low resistance value and introduces virtually no additional load to the input/output buffer circuitry. In a second mode of operation during ESD discharge, the resistive structure has a second significantly higher resistance which reduces current values during the ESD event thereby protecting the buffer circuit. A thick oxide snap-back device is also employed to provide a parallel EDS discharge path with low power dissipation.

Claims

1. An input/output electrostatic discharge protection circuit for protecting semiconductor devices formed on an integrated circuit chip from transient voltage surges which enter through an input/output electrical contact pad on the chip, comprising:

a field effect buffer transistor, electrically coupled between the electrical contact pad and the semiconductor devices to be protected and providing a current path between the electrical contact pad and a chip reference potential, comprising a plurality of discrete field effect transistor segments electrically connected in parallel; and

resistive means, electrically coupled in series between each transistor segment and the electrical contact pad and 15 integrally formed with each field effect transistor segment, for providing an extended resistive path between the electrical contact pad and the transistor segments.

2. An electrostatic discharge protection circuit as set out in claim 1, wherein the total width of the field effect buffer transistor in the direction perpendicular to the direction of current flow is equal to the sum of the widths of the discrete field effect transistor segments.

3. An electrostatic discharge protection circuit as set out in claim 2, wherein the width of each segment is 21 microns or less.

4. An electrostatic discharge protection circuit as set out in claim 3, wherein said buffer transistor comprises 10 segments, each approximately 20μ

in width.

5. An electrostatic discharge protection circuit as set out in claim 1, further comprising means, coupled in parallel with said buffer field effect transistor, for shunting current to said reference potential.

6. An electrostatic discharge protection circuit as set out in claim 5, wherein said means for shunting current comprises a thick oxide field effect transistor structure dimensioned so as to operate in a snap back mode upon occurrence of an electrostatic discharge event.

7. An integrated circuit, having improved resistance to electrostatic discharge events, comprising:

a substrate of semiconductor material having an upper major surface;

an electrical contact pad formed on the upper major surface of said substrate;

a field effect transistor structure formed in the upper major surface of the substrate wherein the field effect structure comprises a plurality of transistor segments each having a source, channel and drain formed in the substrate, and a gate structure formed over the channel region, and wherein the field effect transistor segments extend in a direction perpendicular to the direction of current flow between the source and drain;

a resistive structure formed in said upper major surface of said substrate adjacent to, and integrally coupled with, said discrete transistor segments and extending along the direction perpendicular to current flow; and

a drain contact diffusion formed in said resistive structure and spaced apart from said drain diffusion and electrically connected to said contact pad.

8. An integrated circuit as set out in claim 7, wherein said discrete transistor segments share common source, gate and drain contact electrodes.

9. An integrated circuit as set out in claim 8, wherein said source, drain and drain contact diffusion are n type highly doped silicon and said channel region is p type doped silicon.

10. An integrated circuit as set out in claim 7, wherein said field effect transistor segments are spaced apart in the direction perpendicular to current flow and wherein said resistive structure is a lightly doped diffusion extending in said direction perpendicular to current flow.

11. An integrated circuit as set out in claim 7, wherein the resistive structure is integrally formed with the drain and extends substantially the full width of the field effect transistor structure, whereby the resistive structure is coupled with each field effect transistor segment.

12. An integrated circuit as set out in claim 7, wherein the resistive structure is integrally formed with the drain region and extends substantially the full width of the field effect transistor structure, whereby the resistive structure is coupled with at least two field effect transistor segments and has a recessed region at a gap between the field effect transistor segments with the recessed region narrower than the gap between the field effect transistor segments.

13. An integrated circuit as set out in claim 7, wherein the resistive structure is integrally formed with the drain region and extends substantially the full width of the field effect transistor structure, whereby the resistive structure is coupled with at least two field effect transistor segments and has a recessed region at a gap between the field effect transistor segments with the recessed region wider than the gap between the field effect transistor segments.

14. An integrated circuit as set out in claim 7, further comprising a current shunt device electrically coupled to the electrical contact pad and in parallel with said field effect transistor.

15. An integrated circuit as set out in claim 14, wherein the current shunt devices comprises a gateless field effect transistor formed in said upper major surface of said substrate adjacent to said resistive structure.

16. An integrated circuit, having improved resistance to electrostatic discharge events, comprising:

a substrate of semiconductor material having an upper major surface;

an electrical contact pad formed on the upper major surface of said substrate;

a field effect transistor structure formed in the upper major surface of the substrate wherein the field effect structure comprises a plurality of transistor segments each having a source, channel and drain formed in the substrate, and a gate structure formed over the channel region, and wherein the field effect transistor segments extend in a direction perpendicular to the direction of current flow between the source and drain;

a plurality of discrete resistive structures formed in said upper major surface of said substrate adjacent to each field effect transistor segment, wherein each discrete resistive structure is integrally coupled with one field effect transistor segment and has an extended dimension along the direction perpendicular to current flow; and

a drain contact diffusion formed in each of said resistive structure and spaced apart from said drain diffusion and electrically connected to said contact pad.

17. An integrated circuit as set out in claim 16, further comprising a current shunt device electrically coupled to the electrical contact pad and in parallel with said field effect transistor.

18. An integrated circuit as set out in claim 17, wherein the current shunt devices comprises a gateless field effect transistor formed in said upper major surface of said substrate adjacent to said resistive structure.