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ESD protection circuit with segmented buffer transistor

  • US 5,157,573 A
  • Filed: 01/31/1991
  • Issued: 10/20/1992
  • Est. Priority Date: 05/12/1989
  • Status: Expired due to Term
First Claim
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1. An input/output electrostatic discharge protection circuit for protecting semiconductor devices formed on an integrated circuit chip from transient voltage surges which enter through an input/output electrical contact pad on the chip, comprising:

  • a field effect buffer transistor, electrically coupled between the electrical contact pad and the semiconductor devices to be protected and providing a current path between the electrical contact pad and a chip reference potential, comprising a plurality of discrete field effect transistor segments electrically connected in parallel; and

    resistive means, electrically coupled in series between each transistor segment and the electrical contact pad and 15 integrally formed with each field effect transistor segment, for providing an extended resistive path between the electrical contact pad and the transistor segments.

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