Method and apparatus for locating faults in electronic units

• US 5,157,668 A
• Filed: 07/05/1989
• Issued: 10/20/1992
• Est. Priority Date: 07/05/1989
• Status: Expired due to Fees

• Current Assignee: Bell Seltzer Park & Gibson, PA (Alston & Bird LLP)
• Original Assignee: Applied Diagnostics Incorporated
• Inventors: Rastogi, Ravi, Buenzli, Charles W. Jr., Tayeh, Maurice M., Sierzega, Kenneth F.
• Primary Examiner(s): Beausoliel, Robert W.
• Application Number:
  US07/375,839
• Time in Patent Office: 1,203 Days
• Field of Search: 371/15.1, 371/23, 364/513, 364/200 MS File, 364/900 MS File, 364/488, 364/489, 364/490, 324/158 R
• US Class Current: 714/26
• CPC Class Codes: G01R 31/2846 using hard- or software simulation or using knowledge-based systems, e.g. expert systems, artificial intelligence or interactive algorithms
• CPC Class Codes: G06F 11/2257 using expert systems
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

An artificial intelligence based method and apparatus for locating faults in electronic units includes a technique for modelling electronic units in terms of behavioral constraints. Behavioral constraints model circuit components in terms of changes in outputs thereof which result from changes in inputs thereto. These changes, referred to as "phase changes" may be supplemented by gain and compliance constraints to model an electronic unit at all functional abstraction or hierarchical decomposition levels thereof. In addition to providing a universal modelling scheme, behavioral constraint relationships provide a highly accurate indication of subtle changes in a circuit, for accurate fault location or troubleshooting.

Troubleshooting takes place by applying a predetermined search strategy on the electronic unit which is represented by behavioral constraints. The search strategy begins with a top down search. When a faulty block is found, the search moves down one functional abstraction level and searches the next lower level block having an output corresponding to the output of the higher level block. If the next lower level block is not defective, adjacent blocks at the next lower level are searched.

Testing of the electronic unit is begun according to the functional test plan specified for the unit. Each functional test in the functional test plan is associated with one or more blocks at a functional abstraction level. When a functional test fails, troubleshooting begins at the block and functional abstraction level corresponding to the failed functional test.

Claims

1. A computer based method of characterizing an electronic circuit having a plurality of interconnected electronic circuit components, comprising the steps of:

storing in said computer, a representation of said electronic circuit including said plurality of interconnected electronic circuit components;

determining, for at least one of said electronic circuit components, incremental changes in selected outputs thereof which result from incremental changes in selected inputs thereto; and

storing in said computer, for said at least one of said electronic circuit components, said determined incremental changes in selected outputs thereof which result from said incremental changes in selected inputs thereto;

wherein said at least one of said electronic circuit components include primitive circuit components, and

wherein said at least one of said electronic circuit components further include intermediate and high level circuit components.

2. The method of claim 1 wherein said incremental changes in selected outputs comprise one of an increase and decrease in said selected outputs and wherein said incremental changes in selected inputs comprise one of an increase and decrease in said selected inputs.

3. A computer based method of characterizing an electronic circuit having a plurality of interconnected electronic circuit components, comprising the steps of:

storing in said computer, a representation of said electronic circuit including said plurality of interconnected electronic circuit components;

determining, for at least one of said electronic circuit components, incremental changes in selected outputs thereof which result from incremental changes in selected inputs thereto; and

storing in said computer, for said at least one of said electronic circuit components, said determined incremental changes in selected outputs thereof which result from said incremental changes in selected inputs thereto;

wherein said incremental changes in selected outputs thereof which result from incremental changes in selected inputs thereto comprise a series of IF-THEN statements in the form IF (input change 1, input change 2 . . . input change n) THEN (output change 1, output change 2 . . . output change n), wherein input change 1, input change 2 . . . input change n represent said incremental changes in said selected inputs and output change 1, output change 2 . . . output change n represent said incremental changes in said selected outputs.

4. A computer based method of characterizing an electronic circuit having a plurality of interconnected electronic circuit components, comprising the steps of:

storing in said computer, a representation of said electronic circuit including said plurality of interconnected electronic circuit components;

determining, for at least one of said electronic circuit components, incremental changes in selected outputs thereof which result from incremental changes in selected inputs thereto; and

storing in said computer, for said at least one of said electronic circuit components, said determined incremental changes in selected outputs thereof which result from said incremental changes in selected inputs thereto;

wherein said incremental changes in selected outputs thereof which result from incremental changes in selected inputs thereto comprise a series of statements in the form (input 1, input 2 . . . input n) IN PHASE/OUT OF PHASE (output 1, output 2 . . . output n), where input 1, input 2 . . . input n represent said selected inputs and output 1, output 2 . . . output n represent said selected outputs.

5. A computer based method of characterizing an electronic circuit having a plurality of interconnected electronic circuit components, comprising the steps of:

storing in said computer, a representation of said electronic circuit including said plurality of interconnected electronic circuit components;

determining, for at least one of said electronic circuit components, incremental changes in selected outputs thereof which result from incremental changes in selected inputs thereto;

storing in said computer, for said at least one of said electronic circuit components, said determined incremental changes in selected outputs thereof which result from said incremental changes in selected inputs thereto; and

storing in said computer, for said at least one of said electronic circuit components at least one gain between selected outputs thereof and selected inputs thereof.

6. A computer based method of characterizing an electronic circuit having a plurality of interconnected electronic circuit components, comprising the steps of:

storing in said computer, a representation of said electronic circuit including said plurality of interconnected electronic circuit components;

determining, for at least one of said electronic circuit components, incremental changes in selected outputs thereof which result from incremental changes in selected inputs thereto;

storing in said computer, for said at least one of said electronic circuit components, said determined incremental changes in selected outputs thereof which result from said incremental changes in selected inputs thereto; and

storing in said computer, for at least one of said electronic circuit components at least one compliance thereof.

7. The method of claim 6 wherein said at least one compliance comprises absolute maxima and minima of selected inputs and outputs of said electronic circuit components.

8. The method of claim 6 wherein said at least one compliance comprises a state of said electronic circuit components.

9. A computer based model for circuit components comprising incremental changes in selected outputs of said circuit components which result from incremental changes in selected inputs to said circuit components, said incremental changes in selected outputs and said incremental changes in selected inputs being stored in a computer;

wherein said circuit components include primitive circuit components, and wherein said circuit components further include intermediate and high level circuit components.

10. The model of claim 9 wherein said incremental changes in selected outputs comprise one of an increase and decrease in said selected outputs and wherein said incremental changes in selected inputs comprise one of an increase and decrease in said selected inputs.

11. A computer based model for circuit components comprising incremental changes in selected outputs of said circuit components which result from incremental changes in selected inputs to said circuit components, said incremental changes in selected outputs and said incremental changes in selected inputs being stored in a computer;

wherein said incremental changes in selected outputs which result from incremental changes in selected inputs comprise a series of IF-THEN statements in the form IF (input change 1, input change 2 . . . input change n) THEN (output change 1, output change 2 . . . output change n), wherein input change 1, input change 2 . . . input change n represent said incremental changes in said selected inputs and output change 1, output change 2 . . . output change n represent said incremental changes in said selected outputs.

12. A computer based model for circuit components comprising incremental changes in selected outputs of said circuit components which result from incremental changes in selected inputs to said circuit components, said incremental changes in selected outputs and said incremental changes in selected inputs being stored in a computer;

wherein said incremental changes in selected outputs which result from incremental changes in selected inputs thereto comprise a series of statements in the form (input 1, input 2 . . . input n) IN PHASE/OUT OF PHASE (output 1, output 2 . . . output n), where input 1, input 2 . . . input n represent said selected inputs and output 1, output 2 . . . output n represent said selected outputs.

13. A computer based model for circuit components comprising incremental changes in selected outputs of said circuit components which result from incremental changes in selected inputs to said circuit components, said incremental changes in selected outputs and said incremental changes in selected inputs being stored in a computer and further comprising gains between selected outputs thereof and selected inputs thereof.

14. A computer based model for circuit components comprising incremental changes in selected outputs of said circuit components which result from incremental changes in selected inputs to said circuit components, said incremental changes in selected outputs and said incremental changes in selected inputs being stored in computer and further comprising compliances thereof.

15. The model of claim 14 wherein said compliances comprise absolute maxima and minima of selected inputs and outputs of said circuit components.

16. The model of claim 14 wherein said compliances comprise a state of said circuit components.

17. A computer based method of characterizing an electronic circuit, including a plurality of interconnected electronic components, comprising the steps of:

storing in said computer, a representation of said electronic circuit including said plurality of interconnected electronic components; and

providing a library of models in said computer, said library of models comprising primitive, intermediate and high level models, each of said primitive, intermediate and high level models comprising incremental changes in selected outputs thereof which result from incremental changes in selected inputs thereto.

18. The computer based method of claim 17 further comprising the step of:

associating selected ones of said primitive, intermediate and high level models to characterize said electronic circuit.

19. The method of claim 18 wherein said associating step comprises the steps of:

representing said electronic components in terms of selected ones of said primitive models in said library; and

representing said electronic circuit in terms of selected ones of said intermediate and high level models in said library.

20. The method of claim 19 wherein the step of representing said electronic circuit comprises the steps of:

representing groups of said electronic components in terms of selected ones of said intermediate models in said library; and

representing said plurality of interconnected electronic components in terms of one of said high level models in said library.

21. The method of claim 17 wherein said incremental changes in selected outputs comprise one of an increase and decrease in said selected outputs and wherein said incremental changes in selected inputs comprise one of an increase and decrease in said selected inputs.

22. The method of claim 17 wherein said incremental changes in selected outputs thereof which result from incremental changes in selected inputs thereto comprise a series of IF-THEN statements in the form IF (input change 1, input change 2 . . . input change n) THEN (output change 1, output change 2 . . . output change n), wherein input change 1, input change 2 . . . input change n represent said incremental changes in said selected inputs and output change 1, output change 2 . . . output change n represent said incremental changes in said selected outputs.

23. The method of claim 17 wherein said incremental changes in selected outputs thereof which result from incremental changes in selected inputs thereto comprise a series of statements in the form (input 1, input 2 . . . input n) IN PHASE/OUT OF PHASE (output 1, output 2 . . . output n), where input 1, input 2 . . . input n represent said selected inputs and output 1, output 2 . . . output n represent said selected outputs.

24. The method of claim 17 wherein said models of electronic components further comprise gain between selected outputs thereof and selected inputs thereof.

25. The method of claims 17 or 24 wherein said models of electronic components further comprise compliances thereof.

26. The method of claim 25 wherein said compliances comprise absolute maxima and minima of selected inputs and outputs of said electronic components.

27. The method of claim 25 wherein said compliances comprise a state of said electronic components.

28. A computer based apparatus for characterizing an electronic circuit including a plurality of interconnected electronic components, comprising:

means for storing in said computer, a representation of said electronic circuit including said plurality of interconnected electronic components; and

a library of models in said computer, said library of models comprising primitive, intermediate and high level models, each of said primitive, intermediate and high level models comprising incremental changes in selected outputs thereof which result from incremental changes in selected inputs thereto.

29. The computer based apparatus of claim 28 further comprising:

means for associating selected ones of said primitive, intermediate and high level models to characterize said electronic circuit.

30. The apparatus of claim 28 wherein said incremental changes in selected outputs comprise one of an increase and decrease in said selected outputs and wherein said incremental changes in selected inputs comprise one of an increase and decrease in said selected inputs.

31. The apparatus of claim 28 wherein said incremental changes in selected outputs which result from incremental changes in selected inputs thereto comprise a series of IF-THEN statements in the form IF (input change 1, input change 2 . . . input change n) THEN (output change 1, output change 2 . . . output change n), wherein input change 1, input change 2 . . . input change n represent changes in said selected inputs and output change 1, output change 2 . . . output change n represent changes in said selected outputs.

32. The apparatus of claim 28 wherein said incremental changes in selected outputs which result from incremental changes in selected inputs thereto comprise a series of statements in the form (input 1, input 2 . . . input n) IN PHASE/OUT OF PHASE (output 1, output 2 . . . output n), wherein put 1, input 2 . . . input n represent said selected inputs and output 1, output 2 . . . output n represent said selected outputs.

33. The apparatus of claim 28 wherein said modules of electronic components further comprise gain between selected outputs thereof and selected inputs thereof.

34. The apparatus of claims 28 or 33 wherein said models of electronic components further comprise compliances thereof.

35. The method of claim 34 wherein said compliances comprise absolute maxima and minima of selected inputs and outputs of said electronic components.

36. The method of claim 34 wherein said compliances comprise a state of said electronic components.

37. The apparatus of claim 28 wherein said means for associating comprises:

means for representing said electronic components in terms of selected ones of said primitive models in said library; and

means for representing said plurality of interconnected electronic components in said electronic circuit in terms of selected ones of said intermediate and high level models in said library.

38. The apparatus of claim 37 wherein said means for representing the interconnected electronic components comprises:

means for representing groups of said electronic components in terms of selected ones of said intermediate models in said library; and

means for representing said plurality of interconnected electronic components in terms of one of said high level models in said library.

39. A computer based method for locating a fault in an electronic unit having a plurality of interconnected electronic components, comprising the steps of:

providing a library of models in said computer, said library of models comprising primitive, intermediate and high level models, each of said primitive, intermediate and high level models comprising incremental changes in selected outputs thereof which result from incremental changes in selected inputs thereto;

associated selected ones of said primitive, intermediate and high level models to form a representation of said electronic unit;

obtaining measurements of at least one of said plurality of interconnected electronic components; and

,

employing said representation to determine whether said measurements of said at least one of said plurality of interconnected electronic components result from a malfunction of said at least one of said plurality of interconnected electronic components.

40. The method of claim 39 wherein said primitive, intermediate and high level models further comprise gain between selected outputs thereof and selected inputs thereof.

41. The method of claims 39 or 40 wherein said primitive, intermediate and high level models further comprise compliances thereof.

42. The method of claim 41 wherein said compliances comprise the absolute maxima and minima of selected inputs and outputs thereof.

43. The method of claim 41 wherein said compliances comprise a state of said electronic circuit elements.

44. The method of claim 39 wherein said associating step comprises the steps of:

representing said electronic components in said electronic unit in terms of selected ones of said primitive models in said library and;

representing the interconnected electronic components in said electronic unit in terms of selected ones of said intermediate and high level models in said library.

45. The method of claim 44 wherein the step of representing the interconnected electronic components comprises the steps of:

representing groups of said electronic components in terms of selected ones of said intermediate models in said library; and

representing said plurality of interconnected electronic elements in terms of one of said high level models in said library.

46. The method of claim 39 wherein said obtaining step comprises the step of:

providing an indication of said at least one of said plurality of interconnected electronic components to be measured; and

accepting measurements of said at least one of said plurality of interconnected electronic components.

47. The method of claim 39 wherein said obtaining step comprises the step of:

directing automatic measuring equipment to measure said at least one of said plurality of interconnected components; and

accepting measurements from said automatic measuring equipment.

48. The method of claim 39 wherein said employing step is followed by the step of:

providing an indication that said at least one of said plurality of interconnected components is malfunctioning if it is determined that changes in the outputs of said at least one of said plurality of interconnected electronic components are as a result of a malfunction of said at least one of said plurality of interconnected electronic components.

49. The method of claim 39 wherein said obtaining and employing steps are repeatedly performed on second and subsequent ones of said plurality of interconnected electronic components if it is determined that changes in the outputs of said at least one of said plurality of interconnected electronic components are not as a result of a malfunction of said at least one of said plurality of interconnected electronic components.

50. The method of claim 39 wherein said obtaining and employing steps are repeatedly performed on said at least one of said plurality of interconnected electronic components if it is determined that changes in the outputs of said at least one of said plurality of interconnected electronic components are as a result of a malfunction of said at least one of said plurality of interconnected electronic components, in order to locate the malfunction in one of said at least one of said plurality of interconnected electronic components.

51. The method of claim 50 wherein said intermediate and primitive models are employed during the repeated performance of said obtaining and employing steps in order to locate the malfunction in said one of said plurality of interconnected electronic components.

52. A computer based apparatus for locating a fault in an electronic unit having a plurality of interconnected electronic circuit components, comprising:

means for providing a library of models in said computer, said library of models comprising primitive, intermediate and high level models, each of said primitive, intermediate and high level models comprising incremental changes in selected outputs thereof which result from incremental changes in selected inputs thereto;

means for associating selected ones of said primitive, intermediate and high level models to form a representation of said electronic unit;

means for obtaining measurements of at least one of said plurality of interconnected electronic components; and

,

means connected to said associating means, for determining whether said measurements of said at least one of said plurality of interconnected electronic components are as a result of a malfunction of said at least one of said plurality of interconnected electronic components.

53. The apparatus of claim 52 wherein said primitive, intermediate and high level models further comprise gain between selected outputs thereof and selected inputs thereof.

54. The apparatus of claims 52 or 53 wherein said primitive, intermediate and high level models further comprise compliances thereof.

55. The method of claim 54 wherein said compliances comprise absolute maxima and minima of selected inputs and outputs thereof.

56. The method of claim 54 wherein said compliances comprise a state of said electronic circuit elements.

57. The apparatus of claim 52 wherein said means for associating comprises:

means for representing said electronic components in said electronic unit in terms of selected ones of said primitive models in said library and;

means for representing the interconnected electronic components in said electronic unit in terms of selected ones of said intermediate and high level models in said library.

58. The apparatus of claim 57 wherein said means for representing the interconnected electronic components comprises:

means for representing groups of said electronic components in terms of selected ones of said intermediate models in said library; and

means for representing said electronic unit in terms of one of said high level models in said library.

59. The apparatus of claim 52 wherein said means for obtaining comprises:

means for providing an indication of said at least one of said plurality of interconnected electronic components to be measured; and

means for accepting measurements of said at least one of said plurality of interconnected electronic components.

60. The apparatus of claim 52 wherein said means for obtaining comprises:

means for directing automatic measuring equipment to measure said at least one of said plurality of interconnected components; and

means for accepting measurements from said automatic measuring equipment.

61. The apparatus of claim 52 further comprising:

means for providing an indication that said at least one of said plurality of interconnected components is malfunctioning if it is determined that changes in the outputs of said at least one of said plurality of interconnected electronic components are as a result of a malfunction of said at least one of said plurality of interconnected electronic components.

62. The apparatus of claim 52 wherein said means for obtaining and means for determining repeatedly operate upon second and subsequent ones of said plurality of interconnected electronic elements if it is determined that changes in the outputs of said at least one of said plurality of interconnected electronic components are not as a result of a malfunction of said at least one of said plurality of interconnected electronic components.

63. The apparatus of claim 52 wherein said means for obtaining and means for determining repeatedly operate upon said at least one of said plurality of interconnected electronic components if it is determined that changes in the outputs of said at least one of said plurality of interconnected electronic components are as a result of a malfunction of said at least one of said plurality of interconnected electronic components, in order to locate the malfunction in one of said at least one of said plurality of interconnected electronic components.

64. A computer based method for isolating a fault in a unit under test, said unit under test comprising a plurality of interconnected electronic circuit components, comprising the steps of:

(a) providing in said computer a hierarchical decomposition of said unit under test, said hierarchical decomposition comprising a plurality of blocks each of which includes at least one input and at least one output, said blocks being arranged in a plurality of functional abstraction levels from low to high, each lowest functional abstraction level block corresponding to a respective one of said electronic circuit components, each higher functional abstraction level block including at least one next lower functional abstraction level block;

(b) testing the electronic circuit components corresponding to a selected block to determine if said selected block is faulty;

(c) if said selected block is faulty, testing the electronic circuit components corresponding to a first block in a next lower functional abstraction level from said selected block, said first block having an output which corresponds to an output of said selected block;

(d) if the first block in said next lower functional abstraction level is not faulty, testing the electronic circuit components corresponding to an adjacent block in said next lower functional abstraction level;

(e) repeating step (d) until a faulty next lower functional level block is found;

(f) testing the electronic circuit components corresponding to a second block in a next lower functional abstraction level from said faulty next lower functional level block, said second block having an output which corresponds to an output of said faulty next lower functional abstraction level block; and

(g) repeatedly performing steps (d), (e) and (f) until a faulty circuit component is found.

65. The method of claim 64 wherein said step (c) is preceded by the step of selecting said first block from the set of all blocks in said next lower functional abstraction level having an output which corresponds to an output of said selected block, according to predetermined selection criteria.

66. The method of claim 65 wherein said predetermined selection criteria comprise an ordered list of blocks to be selected, based upon the electronic components included in said blocks.

67. The method of claim 66 wherein said ordered list of blocks to be selected is based upon known failure modes of the electronic elements included in said blocks.

68. The method of claim 64 wherein said adjacent block comprises a block in said next lower functional abstraction level, having an output which corresponds to an input of said first block in said next lower functional abstraction level.

69. The method of claim 64 wherein a prioritized search is performed at said lowest functional abstraction level.

70. The method of claim 64 wherein step (d) is performed if said first block is not faulty, or if it cannot be determined whether said first block is faulty.

71. The method of claim 70 wherein step (f) comprises the step of testing the electronic circuit components corresponding to a second block in a next lower functional level from said faulty next lower level block, or if a faulty next lower level block has not been identified, testing the electronic circuit components corresponding to a second block in a next lower functional level from the block which cannot be determined as faulty.

72. The method of claim 64 wherein said step (b) is preceded by the step of determining a selected block for testing.

73. The method of claim 72 wherein said determining step comprises the steps of:

storing a representation of a functional test plan for said unit under test in said computer, said representation of said functional test plan including a correlation between a respective one of the functional tests and at least one of said plurality of blocks being tested by the respective one of said functional tests; and

applying said functional test plan to said unit under test to determine said selected block.

74. The method of claim 73 wherein said applying step comprises applying the tests specified in said functional test plan to said unit under test, in the order specified by said functional test plan.

75. The method of claim 73 wherein said applying step comprises the steps of:

providing an indication of a functional test to be performed on said unit under test; and

accepting measurements of the results of said functional test.

76. The method of claim 73 wherein said applying step comprises the steps of:

directing automatic test equipment to perform a first functional test on said unit under test; and

accepting the results of said first functional test from said automatic test equipment.

77. The method of claim 64 wherein each of said plurality of blocks in said hierarchical decomposition further comprises incremental changes in selected outputs thereof which result from incremental changes in selected inputs thereto.

78. The method of claim 77 wherein said incremental changes in selected outputs comprise one of an increase and decrease in said selected outputs and wherein said incremental changes in selected inputs comprise one of an incremental increase and decrease in said selected inputs.

79. The method of claim 77 wherein said incremental changes in selected outputs thereof which result from incremental changes in selected inputs thereto comprise a series of IF-THEN statements in the form IF (input change 1, input change 2 . . . input change n) THEN (output change 1, output change 2 . . . output change n), wherein input change 1, input change 2 . . . input change n represent said incremental changes in said selected inputs and output change 1, output change 2 . . . output change n represent said incremental changes in said selected outputs.

80. The method of claim 77 wherein said incremental changes in selected outputs thereof which result from incremental changes in selected inputs thereto comprise a series of statements in the form (input 1, input 2 . . . input n) IN PHASE/OUT OF PHASE (output 1, output 2 . . . output n), where input 1, input 2 . . . input n represent said selected inputs and output 1, output 2 . . . output n represent said selected outputs.

81. The method of claim 80 wherein said models of electronic circuit components further comprise gain between selected outputs thereof and selected inputs thereof.

82. The method of claims 80 or 81 wherein said models of electronic circuit components further comprise compliances thereof.

83. The method of claim 82 wherein said compliances comprise absolute maxima and minima of selected inputs and outputs thereof.

84. The method of claim 82 wherein said compliances comprise a state of said electronic circuit elements.

85. A computer system for isolating a fault in a unit under test, said unit under test comprising a plurality of interconnected electronic circuit components comprising:

means for storing in said computer a hierarchical decomposition of said unit under test, said hierarchical decomposition comprising a plurality of blocks each of which includes at least one input and at least one output, said blocks being arranged in a plurality of functional abstraction levels from low to high, each lowest functional abstraction level corresponding to a respective one of said electronic circuit components, each higher functional abstraction level block including at least one next lower functional abstraction level block;

first means for directing testing of the electronic circuit components corresponding to a selected block to determine if said selected block is faulty;

second means, connected to said first means, for directing testing the electronic circuit components corresponding to a first block in a next lower functional abstraction level from said selected block, said first block having an output which corresponds to an output of said selected block, if said first means indicates that said selected block is faulty; and

third means, connected to said first means, for directing testing of the electronic circuit components corresponding to an adjacent block in said next lower functional abstraction level, if said first means indicates that said selected block is not faulty.

86. The system of claim 85 wherein said first block is selected from the set of all blocks in said next lower functional abstraction level having an output which corresponds to an output of said selected block, according to predetermined selection criteria.

87. The system of claim 86 wherein said predetermined selection criteria comprise an ordered list of blocks to be selected, based upon the electronic components included in said blocks.

88. The system of claim 86 wherein said predetermined selection criteria comprise an ordered list of blocks to be selected, based upon known failure modes of the electronic elements included in said blocks.

89. The system of claim 85 wherein said adjacent block comprises a block in said next lower functional abstraction level, having an output which corresponds to an input of said first block in said next lower functional abstraction level.

90. The system of claim 85 wherein said first means further comprises means for determining said selected block for testing.

91. The system of claim 90 wherein said means for determining comprises:

means for storing a representation of a functional test plan for said unit under test in said computer, said representation of said functional test plan including a correlation between a respective one of the functional tests and at least one of said plurality of blocks being tested by the respective one of said functional tests; and

means for applying said functional test plan to said unit under test to determine said selected block.

92. The system of claim 91 wherein said applying means comprises means for applying the tests specified in said functional test plan to said unit under test, in the order specified by said functional test plan.

93. The system of claim 91 wherein said applying means comprises:

means for providing an indication of a functional test to be performed on said unit under test; and

means for accepting measurements of the results of said functional test.

94. The system of claim 91 wherein said applying means comprises:

means for directing automatic test equipment to perform a first functional test on said unit under test; and

means for accepting the results of said first functional test form said automatic test equipment.

95. The system of claim 85 wherein each of said blocks further comprises incremental changes in selected outputs thereof which result from incremental changes in selected inputs thereto.

96. The system of claim 95 wherein said incremental changes in selected outputs comprise one of an increase and decrease in said selected outputs and wherein said incremental changes in selected inputs comprise one of an increase and decrease in said selected inputs.

97. The system of claim 95 wherein said incremental changes in selected outputs thereof which result from incremental changes in selected inputs thereto comprise a series of IF-THEN statements in the form IF (input change 1, input change 2 . . . input change n) THEN (output change 1, output change 2 . . . output change n), wherein input change 1, input change 2 . . . input change n represent incremental changes in said selected inputs and output change 1, output change 2 . . . output change n represent incremental changes in said selected outputs.

98. The method of claim 95 wherein said incremental changes in selected outputs thereof which result from incremental changes in selected inputs thereto comprise a series of statements in the form (input 1, input 2 . . . input n) IN PHASE/OUT OF PHASE (output 1, output 2 . . . output n), where input 1, input 2 . . . input n represent said selected inputs and output 1, output 2 . . . output n represent said selected outputs.

99. The method of claim 98 wherein said models of electronic circuit components further comprise gain between selected outputs thereof and selected inputs thereof.

100. The method of claims 95 or 98 wherein said models of electronic circuit components further comprise compliances thereof.

101. The method of claim 100 wherein said compliances absolute maxima and minima of selected inputs and outputs thereof.

102. The method of claim 100 wherein said compliances comprise a state of said electronic circuit elements.

103. A computer based method for initiating automated troubleshooting of a unit under test, said unit under test comprising a plurality of interconnected electronic circuit components, said method comprising the steps of:

storing in said computer a hierarchical decomposition of said unit under test, said hierarchical decomposition comprising a plurality of blocks each of which at least one input and at least one output, said blocks being arranged in a plurality of functional abstraction levels from low to high, each lowest functional abstraction level block corresponding to a respective one of said electronic circuit components, each higher functional abstraction level block including at least one next lower functional abstraction level block;

storing a functional test plan for the unit under test in said computer;

associating a respective one of the functional tests in said functional test plan with at least one of said plurality of blocks being tested by the respective one of the functional tests;

causing the functional tests specified in said functional test plan to be performed on said unit under test until one of the functional tests fails; and

,

performing troubleshooting of said electronic circuit components corresponding to the block associated with the failed functional test.

104. The method of claim 103 wherein said causing step comprises the step of:

causing the functional tests specified in said functional test plan to be performed in the sequence specified by said functional test plan.

105. The method of claim 103 wherein said causing step comprises the steps of:

providing an indication of a functional test to be performed on said unit under test; and

accepting measurements of the results of said functional test.

106. The method of claim 103 wherein said causing step comprises the steps of:

directing automatic test equipment to perform a functional test on said unit under test; and

accepting the results of said functional test from said automatic test equipment.

107. A computer based apparatus for initiating automated troubleshooting of a unit under test, said unit under test comprising a plurality of interconnected electronic circuit components, said apparatus comprising:

means for storing in said computer a hierarchical decomposition of said unit under test, said hierarchical decomposition comprising a plurality of blocks each of which includes at least one input and at least one output, said blocks being arranged in a plurality of functional abstraction levels from low to high, each lowest functional abstraction level block corresponding to a respective one of said electronic circuit components, each higher functional abstraction level block including at least one next lower functional abstraction level block;

means for storing a functional test plan for the unit under test in said computer;

means for associating a respective one of the stored functional tests in said functional test plan with at least one of said plurality of blocks being tested by the respective one of the functional tests;

means for causing the functional tests specified in said functional test plan to be performed on said unit under test until one of said functional tests fails; and

,

means for initiating troubleshooting of said electronic circuit components corresponding to the block associated with the failed functional test.

108. The apparatus of claim 107 wherein said means for causing comprises:

means for causing the functional tests specified in said functional test plan to be performed in the sequence specified by said functional test plan.

109. The apparatus of claim 107 wherein said means for causing comprises:

means for providing an indication of a functional test to be performed on said unit under tests; and

means for accepting measurement of the results of said functional test.

110. The apparatus of claim 107 wherein said means for causing comprises:

means for directing automatic test equipment to perform a functional test on said unit under test; and

means for accepting the results of said functional test from said automatic test equipment.

111. A computer system for characterizing an electronic unit comprising a plurality of interconnected electronic circuit components, said computer system comprising:

a circuit knowledge base;

an electronics knowledge base containing models of common electronic circuit components, said models comprising all of phase, gain and compliance limits; and

a knowledge acquisition module connected to said circuit knowledge base and said electronics knowledge base, said knowledge acquisition module comprising;

means for acquiring a representation of a schematic diagram of said electronic unit and placing said schematic diagram representation in said circuit knowledge base;

means for generating a hierarchical decomposition of said electronic unit, said hierarchical decomposition comprising a plurality of blocks each of which includes at least one input and at least one output, said plurality of blocks being organized in a plurality of functional abstraction levels from low to high, the blocks in said lowest functional abstraction level corresponding to a respective one of said electronic circuit components, each higher functional abstraction level block including at least one next lower functional abstraction level block, each of said plurality of blocks corresponding to a model in said electronics database; and

,

means for placing said hierarchical decomposition in said circuit knowledge base.

112. The system of claim 111 wherein said knowledge acquisition module further comprises:

means for acquiring a representation of a test plan for said electronic unit and placing said representation of said test plan in said circuit knowledge base.

113. A computer system for troubleshooting an electronic unit comprising a plurality of interconnected electronic circuit components, said computer system comprising:

a circuit knowledge base, containing a hierarchical decomposition of said unit under test into a plurality of functional abstraction levels;

an electronics knowledge base containing models of common electronic circuit components, said models comprising all of phase, gain and compliance limits; and

a troubleshooting module comprising;

means for storing in said circuit knowledge base a predetermined search strategy for searching said hierarchical decomposition;

means for searching said hierarchical decomposition pursuant to said search strategy; and

means for comparing measurements of said electronic circuit components with said models in said electronics knowledge base, to thereby identify a faulty one of said electronic circuit components.

114. The system of claim 113 wherein said circuit knowledge base further contains a representation of a test plan for said electronic unit, and wherein said means for searching further comprises:

means for causing said test plan to be executed until a failed test is detected; and

means for initiating searching said hierarchical decomposition at a functional abstraction level corresponding to said failed test.