Method and apparatus for performing the square root function using a rectangular aspect ratio multiplier

• US 5,159,566 A
• Filed: 03/13/1992
• Issued: 10/27/1992
• Est. Priority Date: 09/05/1989
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Cyrix Corp (Texas Instruments, Inc.)
• Inventors: Matula, David W., Brightman, Thomas B., Briggs, Willard S.
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US07/852,917
• Time in Patent Office: 228 Days
• Field of Search: 364/752, 364/736
• US Class Current: 708/605
• CPC Class Codes: G06F 7/5525 Roots or inverse roots of single operands

Abstract

A method and apparatus for performing the square root function which first comprises approximating the short reciprocal of the square root of the operand. A reciprocal bias adjustment factor is added to the approximation and the result truncated to form a correctly biased short reciprocal. The short reciprocal is then multiplied by a predetermined number of the most significant bits of the operand and the product is appropriately truncated to generate a first root digit value. The multiplication takes place in a multiplier array having a rectangular aspect raio with the long side having a number of bits essentially as large as the number of bits required for the desired full precision root. The short side of the multiplier array has a number of bits slightly greater by several guard bits than the number of bits required for a single root digit value, which is also determined to be the number of bits in the short reciprocal. The root digit value is squared and the exact square is subtracted from the operand to yield an exact remainder. Succeeding new root digit values are determined by multiplying the short reciprocal by the appropriately shifted current remainder, selectively adding a digit bias adjustment factor and truncating the product. The root digit values are appropriately shifted and accumulated to form a partial root. The described steps are repeated to serially generate root digit values and partial roots with corresponding new exact remainders.

Claims

1. A circuit for calculating an exact square root of an operand, the exact square root comprising a partial root and exact remainder associated with the partial root each comprising a plurality of bits, the circuit comprising:

first storage circuitry for storing the operand;

calculation circuitry having an input coupled to said first storage circuitry for generating more than eight bits of the partial root in a single pass through said calculation circuitry, said more than eight bits operable to be used to calculate remainder bits associated with said more than eight bits and capable of being infinitely precisely rounded, said calculation circuitry further operable to output said more than eight bits through an output of said calculation circuitry;

second storage circuitry coupled to said output of said calculation circuitry and operable to store said more than eight bits; and

said calculation circuitry further operable to calculate said remainder bits using said more than eight bits in a single additional pass through said calculation circuitry, said remainder bits operable to be used to calculate additional bits associated with the exact square root.

2. The circuit of claim 1 wherein said calculation circuitry comprises a multiplier circuit.

3. The circuit of claim 2 wherein said multiplier circuit comprises a multiplier circuit having a rectangular aspect ratio.

4. A method for calculating an exact square root of an operand, the exact square root comprising a partial root comprising a plurality of bits, the method comprising the steps of:

receiving the storing the operand in first storage circuitry;

transmitting signals representing the operand from the first storage circuitry to calculation circuitry having an input coupled to the first storage circuitry;

generating more than eight bits of the partial root in a single pass through the calculation circuitry, the more than eight bits operable to be used to calculate remainder bits associated with the more than eight bits, the more than eight bits capable of being infinitely precisely rounded; and

transmitting signals representing the more than eight bits from the calculation circuitry to second storage circuitry; and

storing the more than eight bits in the second storage circuitry.

5. The method of claim 4 and further comprising the step of generating the remainder bits associated with the more than eight bits using the more than eight bits in a single additional pass through the calculation circuitry, the remainder bits operable to be used to calculate additional bits associated with the exact square root.