×

DRAM architecture having distributed address decoding and timing control

  • US 5,159,572 A
  • Filed: 12/24/1990
  • Issued: 10/27/1992
  • Est. Priority Date: 12/24/1990
  • Status: Expired due to Term
First Claim
Patent Images

1. A DRAM architecture having distributed address decoding and timing control, comprising;

  • a plurality of sections of memory cell arrays forming a plurality of array columns and rows, each memory cell array comprising a plurality of columns and rows of DRAM cells;

    first means positioned adjacent to the sections of memory cell arrays, the first means receiving both an address input and a timing control signal, the first means providing both a partial decode signal and a second signal having both decoding and timing control information, the partial decode and second signals addressing a predetermined section of memory cell arrays at a predetermined time; and

    second means coupled to each memory cell array for receiving both the partial decode signal and the second signal, the second means further decoding the partial decode signal and second signal to provide a select signal to activate a predetermined row of DRAM cells within at least one of the arrays while using the second signal to generate critical timing to accurately control when the predetermined row of DRAM cells is activated regardless of inherent clock skew associated with the timing control signal.

View all claims
  • 7 Assignments
Timeline View
Assignment View
    ×
    ×