DRAM architecture having distributed address decoding and timing control

• US 5,159,572 A
• Filed: 12/24/1990
• Issued: 10/27/1992
• Est. Priority Date: 12/24/1990
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Morton, Bruce L.
• Primary Examiner(s): Laroche, Eugene R.
• Assistant Examiner(s): Nguyen, Tan
• Application Number:
  US07/632,695
• Time in Patent Office: 673 Days
• Field of Search: 365/230.03, 365/230.06, 365/233
• US Class Current: 365/230.06
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A DRAM has both a distributed row address decode and a distributed timing control to generate required timing signals. A level of decoding is implemented within each of local row decoders to generate critical timing signals for each of a plurality of DRAM bit cell arrays. Word line signals from an output of each of the local row decoders are interleaved. The interleaved word line signals permit a high density DRAM semiconductor manufacturing process to utilize a differing pitch for each of a plurality of levels of interconnect. A first level of interconnect has a pitch which is significantly smaller than the pitch of a second interconnect level positioned above the first level of interconnect.

Claims

1. A DRAM architecture having distributed address decoding and timing control, comprising;

a plurality of sections of memory cell arrays forming a plurality of array columns and rows, each memory cell array comprising a plurality of columns and rows of DRAM cells;

first means positioned adjacent to the sections of memory cell arrays, the first means receiving both an address input and a timing control signal, the first means providing both a partial decode signal and a second signal having both decoding and timing control information, the partial decode and second signals addressing a predetermined section of memory cell arrays at a predetermined time; and

second means coupled to each memory cell array for receiving both the partial decode signal and the second signal, the second means further decoding the partial decode signal and second signal to provide a select signal to activate a predetermined row of DRAM cells within at least one of the arrays while using the second signal to generate critical timing to accurately control when the predetermined row of DRAM cells is activated regardless of inherent clock skew associated with the timing control signal.

2. The DRAM architecture of claim 1 wherein the second means further comprise:

a plurality of decoder circuits, each decoder circuit receiving the partial decode signal and the second signal, a predetermined number of the decoder circuits being coupled to two memory cell arrays for selectively providing the select signal to either one of the two memory cell arrays.

3. The DRAM architecture of claim 2 wherein each decoder circuit of the second means is coupled to alternating rows of DRAM cells of a predetermined memory cell array.

4. The DRAM architecture of claim 2 further comprising a first plurality of interconnect conductors for coupling the first partial decode signal and the second signal to the second means, and a second plurality of interconnect conductors for coupling the select signal to the DRAM cells and for coupling the DRAM cells, said first plurality of interconnect conductors having a width which is substantially larger than a width of the second plurality of interconnect conductors.

5. The DRAM architecture of claim 2 wherein each decoder circuit has a length dimension which is an integer multiple larger than a length of an area required to implement a row of the DRAM cells.

6. The DRAM architecture of claim 5 wherein the integer multiple is an even integer multiple.

7. A method of distributing address decoding and timing control in a DRAM, comprising the steps of:

forming a plurality of columns and rows of memory cell arrays within each of a plurality of sections of memory cell arrays, each memory cell array having a plurality of columns and rows of DRAM cells;

positioning first means adjacent each of the sections of memory cell arrays, the first means receiving both an address input and a timing control signal, the first means providing both a partial decode signal and a second signal having both decoding and timing control information, the partial decode and second signals addressing a predetermined section of memory cell arrays at a predetermined time; and

coupling second means to each memory cell array for receiving both the partial decode signal and the second signal, the second means further decoding the partial decode signal and second signal to provide a select signal to activate a predetermined row of DRAM cells within at least one of the arrays while using the second signal to generate critical timing to accurately control when the predetermined row of DRAM cells is activated regardless of inherent clock skew associated with the timing control signal.

8. The method of claim 7 wherein the step of coupling said second means further comprises the steps of:

providing a plurality of decoder circuits, each decoder circuit receiving the partial decode signal and the second signal; and

coupling a predetermined number of the decoder circuits to two memory cell arrays for selectively providing the select signal to either one of the two memory cell arrays.

9. The method of claim 8 wherein the step of coupling a predetermined number of the decoder circuits to two memory cell arrays further comprises the steps of:

coupling the first partial decode signal and the second signal via a first plurality of interconnect conductors;

coupling the DRAM cells and the select signal to the DRAM cells via a second plurality of interconnect conductors; and

forming said first plurality of interconnect conductors having a width which is substantially larger than a width of the second plurality of interconnect conductors.

10. A DRAM architecture having distributed address decoding and timing control, comprising;

an even integer number of sections of memory cell arrays forming a plurality of array columns and rows, each memory cell array comprising a plurality of columns and rows of DRAM cells;

global decoding means positioned adjacent to the sections of memory cell arrays, the global decoding means receiving both an address input and a timing control signal, the global decoding means providing both a partial decode signal and a second signal having both decoding and timing control information, the partial decode and second signals addressing a predetermined section of memory cell arrays at a predetermined time; and

local decoding means comprising a plurality of local decoder circuits positioned adjacent to each memory cell array for receiving both the partial decode signal and the second signal, the local decoding means further decoding the partial decode signal and second signal to provide a select signal to activate a predetermined row of DRAM cells within at least one of the arrays while using the second signal to generate critical timing to accurately control when the predetermined row of DRAM cells is activated regardless of inherent clock skew associated with the timing control signal.

11. The DRAM architecture of claim 10 wherein each local decoder circuit of the local decoding means is coupled to alternating rows of DRAM cells of a predetermined memory cell array in an interleaved manner.