Adaptable MOS current mirror

• US 5,160,899 A
• Filed: 10/22/1991
• Issued: 11/03/1992
• Est. Priority Date: 12/09/1988
• Status: Expired due to Term

• Current Assignee: Synaptics Incorporated
• Original Assignee: Synaptics Incorporated
• Inventors: Allen, Timothy P., Mead, Carver A., Anderson, Janeen D. W., Wall, Michael F.
• Primary Examiner(s): Mullins, James B.
• Application Number:
  US07/781,503
• Time in Patent Office: 378 Days
• Field of Search: 330/277, 330/288, 330/307, 307/246, 307/350, 307/351, 323/315-317
• US Class Current: 330/288
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H03F 1/0261 with control of the polarisation voltage or current, e.g. gliding Class A
• CPC Class Codes: H03F 1/303 using a switching device H03F1/305, H03F3/005, H03F3/38 take precedence
• CPC Class Codes: H03F 3/45479 characterised by the way of common mode signal rejection
• CPC Class Codes: H03F 3/45753 using switching means, e.g. sample and hold
• CPC Class Codes: H03F 3/45977 using switching means, e.g. sample and hold

Abstract

An adaptable current mirror includes first and second MOS transistors. The first MOS transistor has its gate connected to its drain. A MOS capacitor structure is connected in series between the gate of the first MOS transistor and the gate of the second MOS transistor. Electrons may be placed onto and removed in an analog manner from a floating node associated with the second MOS transistor, usually the gate of the transistor, by application of first and second electrical control signals. A first electrical control signal controls the injection of electrons onto the floating node from an electron injection structure and the second electrical control signal controls the removal of electrons from the floating node by an electron removal structure. A plurality of adaptable current mirrors communicating with a plurality of current-carrying lines may be employed for indicating the output of the one of the plurality of current-carrying lines through which the most current is flowing.

Claims

1. An adaptable MOS current mirror fabricated on a semiconductor substrate, said adaptable MOS current mirror having an input node and an output node and including:

first and second MOS transistors, each having a source, a gate, and a drain;

a first MOS capacitor having first and second electrodes;

the source of said first MOS transistor being connected to a source of fixed voltage, the gate and drain of said first MOS transistor being connected to said input node and to said first electrode of said first MOS capacitor, the source of said second MOS transistor being connected to a source of fixed voltage, the gate of said MOS transistor comprising a floating node connected to said second electrode of said first capacitor, the drain of said second MOS transistor forming said output node;

means for generating a first electrical control signal;

electron removal means coupled to said floating node and responsive to said means for generating said first electrical control signal, for removing electrons from said floating node, said electron removal means operating to vary the rate of removal of electrons from said floating gate in response to the magnitude of said first electrical control signal;

means for selectively supplying a calibration current to said input node during adaptation;

means for generating a second electrical control signal during adaptation;

electron injecting means coupled to said floating node and responsive to said second electrical control signal for injecting electrons on to said floating node, said electron injecting means operating to vary the rate of injection of electrons on to said floating node in response to the magnitude of said second electrical control signal;

whereby the output current of said current mirror is adapted to be equal to said desired output current when its input current is equal to said calibration current.

2. The adaptable MOS current mirror of claim 1 wherein said electron injecting means is a non-avalanche hot electron injection device including:

a p-type region in said semiconductor substrate,

an n-type region disposed in said p-type region,

a floating gate disposed above said p-type region, said floating gate at least partially overlapping one edge of said n-type region and separated from the surface of said substrate by a gate oxide under a portion of said floating gate including at least where it partially overlaps the edge of said n-type region,

means for applying a negative potential to said p-region, said negative potential having a magnitude of greater than about 3.2 volts relative to said floating gate,

means for applying a positive potential to said n-type region with respect to said p-type region to reverse bias said n-type region, said positive potential having a magnitude greater than about 3.2 volts relative to said p-type region, but less than the voltage required to induce avalanche breakdown between said n-type region and said p-type region,

means for injecting electrons into said p-type region,

whereby said first and second positive potentials act to accelerate said electrons to an energy sufficient to surmount the barrier energy of said gate oxide and thereby inject said electrons onto said floating gate.

3. The adaptable MOS current mirror of claim 1 wherein said second control signal is a monotonic function of the difference between the actual output current of said current mirror and said desired output current, whereby said adaptable current mirror operates to make said actual output current equal to said desired output current.

4. The adaptable MOS current mirror of claim 1 wherein said electron removal means comprises an electron tunneling device having an anode connected to said means for generating a first control signal and a cathode connected to said floating node and wherein said electron injecting means comprises a gated-bipolar transistor having a gate connected to said floating node, a collector connected to a first source of electrical potential, an emitter connected to a second source of electrical potential, said second source of electrical potential having a magnitude less than that of said first source of electrical potential, and a base connected to said means for generating a second control signal.

5. An adaptable circuit, communicating with a plurality of current-carrying lines, for indicating the output of the one of said plurality of current-carrying lines through which the most current is flowing, including:

a plurality of capacitor coupled MOS current mirrors, each of said current mirrors including an input node, an output node, a driving MOS current mirror transistor and a driven MOS current mirror transistor, the sources of each driving MOS current mirror transistor and each driven MOS current mirror transistor connected to a source of fixed positive voltage, the gate and drain of each of said driving MOS current mirror transistors comprising said input node and connected to a different one of said current carrying lines and to a first electrode of an MOS capacitor, the gate of said driven MOS current mirror transistor connected to a floating node, the second electrode of said MOS capacitor comprising a portion of said floating node, and the drain of said driven MOS current mirror transistor comprising said output node;

a pulldown transistor associated with each of said current mirrors, each of said pulldown transistors having its source connected to a source of fixed negative voltage, and its gate connected to a common pulldown gate line;

a pulldown gate bias transistor, having its source connected to said source of negative voltage, its gate connected to a source of bias voltage;

a follower transistor associated with each of said current mirrors, each of said follower transistors having its gate connected to the output of the current mirror with which it is associated, and having a source-drain path connected between a source of fixed voltage and said common pulldown gate line;

means, operable during an operating mode of said circuit, for selectively connecting the drain of said pulldown gate bias transistor to said common pulldown gate line, and for enabling said source-drain path of each said follower transistor;

means, operable during an adapting mode of said circuit, for selectively connecting said common pulldown gate line to a source of fixed voltage, for disabling said source-drain path of said follower transistor, and for adjusting the charge on each floating node in response to the voltage at said output node of said current mirror with which it is associated;

whereby the offset voltages of said circuit can be adapted during said adapting mode of said circuit.