Field-programmable redundancy apparatus for memory arrays

• US 5,161,157 A
• Filed: 11/27/1991
• Issued: 11/03/1992
• Est. Priority Date: 03/12/1990
• Status: Expired due to Term

• Current Assignee: Xicor LLC (Renesas Electronics Corporation)
• Original Assignee: Xicor LLC (Renesas Electronics Corporation)
• Inventors: Wang, Ping, Owen, William H., Nojima, Isao, Drori, Joseph, Caywood, John, Jaffe, James, Sung, Jeffrey
• Primary Examiner(s): Beausoliel, Robert W.
• Assistant Examiner(s): LO, ALLEN
• Application Number:
  US07/802,005
• Time in Patent Office: 342 Days
• Field of Search: 371/10.3, 371/10.2, 371/10.1, 371/11.1, 365/200
• US Class Current: 714/710
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G11C 29/789 using non-volatile cells or latches
• CPC Class Codes: G11C 29/835 with roll call arrangements for redundant substitutions
• CPC Class Codes: G11C 29/838 with substitution of defective spares

Abstract

A field-programmable redundancy apparatus for integrated circuit semiconductor memory arrays is disclosed. The present invention allows the user to replace a defective memory cell with a redundant memory cell while the integrated circuit memory array is in the field. The user communicates with the redundancy apparatus over standard signal paths of the integrated circuit semiconductor memory array and with standard voltage levels. The redundancy apparatus detects a predetermined code sequence on one or more of the address and data lines of the memory array to enter a special redundancy-reconfiguration mode. In the reconfiguration mode, the redundancy apparatus provides information on the availability and functionality of the redundant memory cells and enables the user to replace a defective memory cell with a selected redundant memory cell. The field-programmable redundancy apparatus may comprise nonvolatile memory means, such as EEPROM'"'"'s, to store the replacements of primary memory cells with redundant memory cells. In the reconfiguration mode, detection of a second predetermined code sequence causes the reconfiguration mode to be exited.

Claims

1. In an integrated circuit memory array including a plurality of primary memory cells, each said primary memory cell for storing data, a redundant memory cell for storing data, address means for enabling each of said primary memory cells to be accessed when a corresponding unique address is coupled thereto on a plurality of address lines, said address means using standard binary logic voltage levels when coupling said unique address onto said address lines, and binary logic voltage levels when coupling said unique address onto said address lines, and read/write means for reading data from and for writing data to each said primary memory cell on a plurality of data lines when the address of said primary memory cell is coupled to said address means, said read/write means using standard binary logic voltage levels for data states on said data lines, a field-programmable redundancy system for enabling said integrated circuit memory array to temporarily enter a special reconfiguration mode for replacing a selected one of said primary memory cells with said redundant memory cell such that data is exchanged by said read/write means with said redundant memory cell when the address of said replaced primary memory cell is coupled to said address means, comprising:

means for detecting a predetermined code sequence on one or more of said address and data lines;

means for causing said integrated circuit memory array to enter said reconfiguration mode when said predetermined code sequence is detected;

means responsive to said entry into said reconfiguration mode for disabling normal accessing of said primary memory cells by said address means and said read/write means;

means during said reconfiguration mode for receiving the address of a selected primary memory cell to be replaced by said redundant memory cell;

reconfiguration means responsive to said receiving means during said reconfiguration mode for replacing said selected primary memory cell with said redundant memory cell such that said redundant memory cell is thereafter accessed when the address of said selected primary memory cell is coupled to said address means; and

means for causing said integrated circuit memory array to exit said reconfiguration mode.

2. The field-programmable redundancy system of claim 1 wherein said reconfiguration means comprises means for detecting the address of a selected primary memory cell currently replaced by said redundant memory cell and reset means responsive to said detecting means for undoing said replacement of said selected primary

3. The field-programmable redundancy system of claim 1 wherein said reconfiguration means includes means for storing the address of the primary memory cell currently replaced by said redundant memory cell in a non-voltage memory.

4. The field-programmable redundancy system of claim 1 wherein said means for causing said integrated circuit memory array to exit said reconfiguration mode includes means for detecting a second predetermined code sequence on one or more of said address and data lines.

5. The field-programmable redundancy system of claim 1 wherein said reconfiguration means includes a redundancy decoder responsive to signals on one or more of said address lines for selectively addressing said redundant memory cell, said redundancy decoder including a redundant cell decoder responsive to a predetermined address on said address lines for accessing said redundant memory cell.

6. The field-programmable redundancy system of claim 5 wherein said redundant cell decoder comprises:

a first non-volatile memory for storing the address of a primary memory cell;

a second non-volatile memory for storing the status of said redundant memory cell as being in use when said redundant memory cell is being used as a replacement memory cell for one of said primary memory cells;

means for detecting a match condition between the primary memory cell address appearing on said address lines and the address stored in said first non-volatile memory and for outputting a match condition signal only when said second non-volatile memory indicates said redundant memory cell is in use; and

means responsive to said match condition signal when said integrated circuit memory array is not in said reconfiguration mode for disabling the addressing of said replaced primary memory cell and for enabling the address of said redundant memory cell.

7. The field-programmable redundancy system of claim 6 further comprising means responsive to a given primary memory cell address appearing on said address lines for outputting a match condition signal on one or more of said data lines when the primary memory cell specified by said address has been replaced by said redundant memory cell.

8. The field-programmable redundancy system of claim 6 wherein said redundant cell decoder further includes a third nonvolatile memory for storing the status of said redundant memory cell as being non-functional.

9. The field-programmable redundancy system of claim 8 further comprising means responsive to said third memory for outputting said non-functional status of said redundant memory cell on said data lines.

10. The field-programmable redundancy system of claim 6 wherein each of said primary memory cells comprises a plurality of memory bits equal to a predetermined number, said memory bits of said primary memory cell organized as a row and called a primary memory row, and wherein said redundant memory cell comprises a plurality of memory bits equal to said predetermined number, said memory bits of said redundant memory cell organized as a row and called a redundant memory row.

11. The field-programmable redundancy system of claim 10 wherein said read/write means comprises a plurality of column bit lines for each said data line, the total of said column bit lines equal to said predetermined number of memory bits of each said primary memory row, and wherein each said column bit line is coupled to one memory bit of each of said primary memory rows such that data can be exchanged between said one memory bit and said read/write means.

12. The field-programmable redundancy system of claim 11 wherein a number of said plurality of address lines of said address means are used to address said primary rows and are designed as row address lines, and wherein the remainder of said plurality of address lines of said address means are used to address said column bit lines of each said data line and are designated as column address lines.

13. The field-programmable redundancy system of claim 6 wherein said reconfiguration means includes:

means for programming said first non-volatile memory of said redundant cell decoder during said reconfiguration mode with the address of the primary memory cell to be replaced by said redundant memory cell; and

means for programming said second non-volatile memory of said redundant cell decoder during said reconfiguration mode to indicate said redundant memory cell is in use.

14. The field-programmable redundancy system of claim 6 wherein said first non-volatile memory of said redundant cell decoder comprises one or more memory bits, each said memory bit comprising at least one EEPROM cell.

15. The field-programmable redundancy system of claim 1 wherein said read/write means includes means responsive to a plurality of control signals for controlling whether said integrated circuit memory array performs a read operation or write operation to an addressed memory cell, said read/write means detecting standard binary degree voltage levels for the control signal states provided thereto.

16. In an integrated circuit memory array having a plurality of primary memory cells and a redundant memory cell, address lines for selectively addressing each of said primary memory cells and one or more data lines for writing of data to or read out of data from each said primary memory cell when that cell has been selectively addressed, a method for replacing a defective one of said primary memory cells with said redundant memory cell comprising the steps of:

detecting a first predetermined code sequence on one or more of said address and data lines of said integrated circuit memory array;

causing said integrated circuit memory array to enter a reconfiguration mode of operation when said first predetermined code sequence is detected;

replacing said defective primary cell with said redundant cell in said reconfiguration mode such that said redundant memory cell is accessed for data transfer on said data lines when the address of said defective primary memory cell is thereafter placed on said address lines; and

causing said integrated circuit memory array to exit said reconfiguration mode of operation when a second predetermined code sequence is detected on one or more of said address and data lines.

17. In an integrated circuit memory array including a plurality of primary memory cells, each said primary memory cell for storing data, at least one redundant memory cell for storing data, address means for enabling each of said primary memory cells to be accessed when a corresponding unique address is coupled thereto on a plurality of address lines, said address means using standard binary logic voltage levels when coupling said unique address onto said address lines, and read/write means for reading data from and for writing data to each said primary memory cell on a plurality of data lines when the address of said primary memory cell is coupled to said address means, said read/write means using standard binary logic voltage levels for data states on said data lines, a field-programmable redundancy system for enabling said integrated circuit memory array to temporarily enter a special reconfiguration mode for replacing a selected one of said primary memory cells with one of said redundant memory cells such that data is exchanged by said read/write means with said redundant memory cell when the address of said replaced primary memory cell is coupled to said address means, comprising:

means for detecting a predetermined code sequence on one or more of said address and data lines;

means for causing said integrated circuit memory array to enter said reconfiguration mode when said predetermined code sequence is detected;

means responsive to said entry into said reconfiguration mode for disabling normal accessing of said primary memory cells by said address means and said read/write means;

means for providing a unique predetermined address for each o said redundant memory cells;

means during said reconfiguration mode for receiving the address of a selected primary memory cell to be replaced by a redundant memory cell and for receiving the address of a selected redundant memory cell to be used to replace said selected primary memory cell;

reconfiguration means responsive to said receiving means during said reconfiguration mode for replacing said selected primary memory cell with said selected redundant memory cell such that said selected redundant memory cell is thereafter accessed when the address of said selected primary memory cell is coupled to said address means; and

means for causing said integrated circuit memory array to exit said reconfiguration mode.

18. The field-programmable redundancy system of claim 17 further comprising means for identifying which of said redundant memory cells are available for use and means for coupling the identity of each said available redundant memory cell to said read/write means.

19. The field-programmable redundancy system of claim 17 under comprising means for determining which of said redundant memory cells are currently in use and means for coupling the identity of redundant memory cells not currently in use to said read/write means.

20. The field-programmable redundancy system of claim 17 further comprising means for determining if a selected primary memory cell is currently replaced by a redundant memory cell when the address of said selected primary memory cell is coupled to said address means, including means for coupling the address of said redundant memory cell to said read/write means.

21. The field-programmable redundancy system of claim 17 wherein said reconfiguration means further comprises means for replacing a first redundant memory cell which had previously replaced a selected primary memory cell with a second redundant memory cell.

22. The field-programmable redundancy system of claim 21 wherein said reconfiguration means causes said first redundant cell to be marked as non-functional.

23. The field-programmable redundancy system of claim 17 wherein said reconfiguration means comprises means for detecting the address of a selected primary memory cell currently replaced by a redundant memory cell and reset means responsive to said detecting means for undoing said replacement of said selected primary memory cell.

24. The field-programmable redundancy system of claim 17 wherein said reconfiguration means includes means for storing the address of each primary memory cell currently replaced by a redundant memory cell in a non-volatile memory.

25. The field-programmable redundancy system of claim 17 wherein said means for causing said integrated circuit memory array to exit said reconfiguration mode includes means for detecting a second predetermined code sequence on one or more of said address and data lines.

26. The field-programmable redundancy system of claim 17 wherein said reconfiguration means includes a redundancy decoder responsive to signals on one or more of said address lines for selectively addressing each of said redundant memory cells, said redundancy decoder including a plurality of redundant cell decoders, each said redundant cell decoder responsive to a predetermined address on said address lines for accessing a corresponding one of said redundant memory cells.

27. The field-programmable redundancy system of claim 26 wherein each said redundant cell decoder comprises:

a first non-volatile memory for storing the address of a primary memory cell;

a second non-volatile memory for storing the status of said corresponding redundant memory cell as being in use when said redundant memory cell is being used as a replacement memory cell for one of said primary memory cells;

means for detecting a match condition between the primary memory cell address appearing on said address lines and the address stored in said first non-volatile memory and for outputting a match condition signal only when said second non-volatile memory indicates said corresponding redundant memory cell is in use; and

means responsive to said match condition signal when said integrated circuit memory array is not in said reconfiguration mode for disabling the addressing of said replaced primary memory cell and for enabling the addressing of the redundant memory cell corresponding to said redundant cell decoder.

28. The field-programmable redundancy system of claim 27 further comprising means responsive to a given primary memory cell address appearing on said address lines for outputting a match condition signal or one or more of said data lines when the primary memory cell specified by said address has been replaced by one of said redundant memory cells, and for outputting on said data lines the identify of said one of said redundant memory cells replacing said specified primary memory cell.

29. The field-programmable redundancy system of claim 27 wherein each said redundant cell decoder further includes a third nonvolatile memory for storing the status of said corresponding redundant memory cell as being non-functional.

30. The field-programmable redundancy system of claim 29 further comprising means corresponding to each said redundant cell decoder and responsive to the corresponding third memory for outputting said non-functional status of said corresponding redundant memory cell on said data lines.

31. The field-programmable redundancy system of claim 27 wherein each of said primary memory cells comprises a plurality of memory bits equal to a predetermined number, said memory bits of said primary memory cell organized as a row and called a primary memory row, and wherein each of said redundant memory cells comprises a plurality of memory bits equal to said predetermined number, said memory bits of said redundant memory cell organized as a row and called a redundant memory row.

32. The field-programmable redundancy system of claim 31 wherein said read/write means comprises a plurality of column bit lines for each said data line, the total of said column bit lines equal to said predetermined number of memory bits of each said primary memory row, and wherein each said column bit line is coupled to one memory bit of each of said primary memory rows such that data can be exchanged between said one memory bit and said read/write means.

33. The field-programmable redundancy system of claim 32 wherein a number of said plurality of address lines of said address means are used to address said primary rows and are designated as row address lines, and wherein the remainder of said plurality of address lines of said address means are used to address said column bit lines of each said data line and are designated as column address lines.

34. The field-programmable redundancy system of claim 27 wherein said reconfiguration means includes:

means for programing each of said first non-volatile memories of said redundant cell decoders during said reconfiguration mode such that the first non-volatile memory in a selected redundant cell decoder is programmed with the address of the primary memory cell to be replaced by the redundant memory cell corresponding to said selected redundant cell decoder; and

means for programming each of said second non-volatile memories of said redundant cell decoders during said reconfiguration mode to indicate for each said redundant cell decoder that its corresponding redundant memory cell is in use.

35. The field-programmable redundancy system of claim 27 wherein each of said first non-volatile memories of said redundant cell decoders comprises one or more memory bits, each said memory bit comprising at least one EEPROM cell.

36. The field-programmable redundancy system of claim 17 wherein said read/write means includes means responsive to a plurality of control signals for controlling whether said integrated circuit memory array performs a read operation or a write operation to an addressed memory cell, said read/write means detecting standard binary logic voltage levels for the control signal states provided thereto.

37. In an integrated circuit memory array having a plurality of primary memory cells and at least one redundant memory cell, address lines for selectively addressing each of said primary memory cells and one or more data lines for writing of data to or reading out of data from each said primary memory cell when that cell has been selectively addressed, a method for replacing a defective one of said primary memory cells with a selected one of said redundant memory cells comprising the steps of:

detecting a first predetermined code sequence on one or more of said address and data lines of said integrated circuit memory array;

causing said integrated circuit memory array to enter a reconfiguration mode of operation when said first predetermined code sequence is detected;

replacing said defective primary cell with said selected redundant cell in said reconfiguration mode such that said selected redundant memory cell is accessed for data transfer on said data lines when the address of said defective primary memory cell is thereafter placed on said address lines; and

causing said integrated circuit memory array to exit said reconfiguration mode of operation when a second predetermined code sequence is detected on one or more of said address and data lines.