Semiconductor memory with multiple clocking for test mode entry

• US 5,161,159 A
• Filed: 08/17/1990
• Issued: 11/03/1992
• Est. Priority Date: 08/17/1990
• Status: Expired due to Term

• Current Assignee: SGS Thomson Microelectronics Inc (STMicroelectronics NV), Wisconsin Alumni Research Foundation (University of Wisconsin System)
• Original Assignee: SGS Thomson Microelectronics Inc (STMicroelectronics NV)
• Inventors: McClure, David C., Coker, Thomas A.
• Primary Examiner(s): BEAUSOLIEL JR, ROBERT W
• Application Number:
  US07/568,968
• Time in Patent Office: 809 Days
• Field of Search: 371/22.1, 371/15.1, 371/21.1, 371/21.4, 324/158 R, 324/158 T, 324/73.1, 365/201
• US Class Current: 714/724
• CPC Class Codes: G01R 31/31701 Arrangements for setting the Unit Under Test [UUT] in a test mode
• CPC Class Codes: G11C 29/46 Test trigger logic

Abstract

An integrated circuit having a normal operating mode and a special operating mode, such as a special test mode, is disclosed. The special test mode is enabled by a series of signals, such as overvoltage excursions at a terminal, rather than by a single such excursion, so that it is less likely that the special test mode is entered inadvertently, such as due to noise or power-down and power-up of the device. The circuit for enabling the test mode includes a series of D-type flip-flops, each of which are clocked upon detection of the overvoltage condition together with a particular logic level applied at another terminal; multiple series of flip-flops may be provided for multiple special test modes. Additional features include the provision of a power-on reset circuit which locks out the entry into the test mode during power-up of the device. Acknowledgment of the entry into test mode is provided by the presentation of a low impedance at output terminals while the device is not enabled; chip enable of the device causes the device to exit the test mode. Once in test mode, the output enable terminal of the device can provide a chip enable function.

Claims

1. An integrated circuit having a normal operating mode, and having a special operating mode enabled by an enable signal, comprising:

a first terminal for receiving pulses of a mode initiate signal indicating entry into a special operating mode; and

an enable circuit, having an input coupled to said first terminal, and having an output for presenting said enable signal responsive to receipt, at said first terminal, of a plurality of pulses of said mode initiate signal, wherein said enable circuit comprises sequential logic for storing a state indicating the receipt of a single pulse of said mode initiate signal and for not presenting said enable signal responsive to receipt, at said first terminal, of a signal pulse of said mode initiate signal.

2. The circuit of claim 1, wherein said enable circuit comprises:

a plurality of latch circuits, each clocked responsive to receipt of a pulse of said mode initiate signal, wherein the output of a last one of said latch circuits presents said enable signal, and wherein said plurality of latch circuits are connected in series in such a manner that the last one of said latch circuits presents said enable signal responsive to receipt of a plurality of pulses of said mode initiate signal.

3. The circuit of claim 2, wherein each of said plurality of latch circuits have a preferred state on power-up of the circuit in such a manner as to indicate that no pulses of said mode initiate signal have been received.

4. The circuit of claim 1, further comprising:

a second terminal, for receiving a mode select signal;

an evaluation circuit, for coupling said first and second terminals to said enable circuit by having inputs coupled to said first and second terminals and having an output coupled to said input of said enable circuit, and for presenting a match signal to said enable circuit responsive to the receipt of a pulse of said mode initiate signal in conjunction with said mode select signal.

5. The circuit of claim 4, wherein said second terminal receives first and second mode select signals, for selecting first and second special operating modes;

and wherein said evaluation circuit presents, at its output, first and second match signals responsive to the receipt of a pulse of said mode initiate signal in conjunction with said first and second mode select signals, respectively.

6. The circuit of claim 5, wherein said enable circuit comprises:

a first enable circuit, having an input coupled to the output of said evaluation circuit, and having an output for presenting a first enable signal responsive to receipt of a plurality of said first match signals, wherein said first enable circuit comprises sequential logic for storing a state indicating the receipt of a single first match signal and for not presenting said first enable signal responsive to receipt of a single first match signal; and

a second enable circuit, having an input coupled to the output of said evaluation circuit, and having an output for presenting a second enable signal responsive to receipt of a plurality of said second match signals, wherein said second enable circuit comprises sequential logic for storing a state indicating the receipt of a single second match signal and for not presenting said second enable signal responsive to receipt of a single second match signal.

7. The circuit of claim 6, wherein said first enable circuit comprises:

a plurality of latch circuits clocked responsive to receipt of said first match signals, wherein the output of a last one of said latch circuits presents said first enable signal, and wherein said plurality of latch circuits are connected in series in such a manner that the last one of said latch circuits presents said first enable signal responsive to receipt of a plurality of said first match signals;

and wherein said second enable circuit comprises;

a plurality of latch circuits clocked responsive to receipt of said second match signals, wherein the output of a last one of said latch circuits presents said second enable signal, and wherein said plurality of latch circuits are connected in series in such a manner that the last one of said latch circuits presents said second enable signal responsive to receipt of a plurality of said second match signals.

8. The circuit of claim 7, further comprising:

a functional circuit coupled to said first terminal;

wherein said functional circuit responds to signals having an amplitude in a range between first and second limits when the circuit is in a normal operating mode;

and wherein said mode initiate signal received at said first terminal comprises a pulse having an amplitude outside of said range.

9. The circuit of claim 8, further comprising:

an overvoltage detection circuit, coupled between said first terminal and said evaluation circuit, for detecting receipt of said mode initiate signal at said first terminal.

10. The circuit of claim 1, further comprising:

a functional circuit coupled to said first terminal;

wherein said functional circuit responds to signals having an amplitude in a range between first and second limits when the circuit is in a normal operating mode;

and wherein said mode initiate signal received at said first terminal comprises a pulse having an amplitude outside of said range.

11. The circuit of claim 10, further comprising:

an overvoltage detection circuit, coupled between said first terminal and said enable circuit, for detecting receipt of said mode initiate signal at said first terminal.

12. A method for enabling a special operating mode of a circuit, comprising:

receiving a plurality of mode initiate pulses at a first terminal of said circuit; and

generating a special mode enable signal responsive to receipt of said plurality of mode initiate pulses, wherein said special mode enable signal is not generated responsive to receipt of a single one of said plurality of mode initiate pulses.

13. The method of claim 12, wherein, in a normal operating mode, said circuit is responsive to signals received at said first terminal having an amplitude in a range between first and second limits.

15. The method of claim 12, wherein the step of generating the special mode enable signal comprises:

clocking a series of latches responsive to receipt of each of said mod initiate pulses.

16. The method of claim 15, wherein the step of generating the special mode enable signal further comprises:

presenting a data state to the first one of said series of latches so that said data state is clocked into said first one of said series of latches responsive to receipt of a first one of said plurality of mode initiate pulses;

and wherein said series of latches are connected in series in such a manner that the last one of said series of latches presents the special mode enable signal at its output after said clocking step has been performed for said plurality of mode initiate pulses.

14. The method of clam 13, wherein each of said plurality of mode initiate pulses comprises a signal having an amplitude outside of said range.

17. A circuit for enabling a special operating mode, comprising:

a first terminal;

a plurality of latches connected in series with one another, a first one of said plurality of latches having a known logic state connected to its data input, and a last one of said plurality of latches generating an enable output at its output;

a clocking circuit coupled to said first terminal and to clock inputs of said plurality of latches, for presenting a clock signal to said plurality of latches responsive to receipt of a mode initiate signal at said first terminal.

18. The circuit of claim 17, further comprising:

an overvoltage detector circuit, coupled between said first terminal and said clocking circuit;

wherein said clocking circuit presents a clock signal responsive to said overvoltage detector circuit detecting an overvoltage condition at said first terminal.

19. The circuit of claim 18, wherein a functional circuit is connected to said first terminal, said functional circuit responsive to signals at said first terminal having an amplitude in a range between first and second limits;

and wherein signals at said first terminal in said range do not present an overvoltage condition detected by said overvoltage detector circuit.

20. The circuit of claim 18, further comprising:

a second terminal;

wherein said clocking circuit is coupled to said second terminal, and presents clock signals to said plurality of latches responsive to receiving a first code signal at said second terminal in conjunction with said mode initiate signal.

21. The circuit of claim 17, wherein each of said plurality of latches have a preferred state on power-up of the circuit in such a manner as to indicate that no mode initiate signals has been received.