Microprocessor inverse processor state usage

• US 5,161,226 A
• Filed: 05/10/1991
• Issued: 11/03/1992
• Est. Priority Date: 05/10/1991
• Status: Expired due to Fees

• Current Assignee: JMI Software Systems Incorporated
• Original Assignee: JMI Software Consultants, Inc.
• Inventors: Wainer, Susan E.
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US07/698,077
• Time in Patent Office: 543 Days
• Field of Search: 364/DIG. 1, 364/DIG. 2, 395/650, 395/725
• US Class Current: 710/264
• CPC Class Codes: G06F 9/463 Program control block organisation
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked

Abstract

A method for operating a multi-tasking, interrupt capable microprocessor under inverse processor state usage is provided whereby the effective time for both interrupt processing and switching context between task execution and interrupt processing is reduced, thereby significantly enhancing the overall performance of the operating system kernel. This increased performance is achieved by the elimination of the previously needed temporary storage in memory of volatile global registers and task context data. Volatile global registers are preserved in local registers during interrupt processing, thereby eliminating time-consuming transfers of data to and from temporary memory storage locations. A task procedure stack, rather than the interrupt stack, is utilized for interrupt records and frames containing user task context data. This is accomplished by programmably creating an inverse processor state designation. Therefore, the requirements to move this data between locations in memory as would otherwise be required is eliminated when performing context switches during interrupt processing.

Claims

1. A method of "inside-out", inverse operation of operating a multi-tasking, interrupt capable microprocessor system having a user memory stack, an interrupt stack, an interrupt handler mechanism, a register set, and a process-controls register with a state bit defining the operational state of said microprocessor and designating an execute state and an interrupt state, and is comprised of the following steps:

entering a user task;

setting said state bit to the inverse value of the microprocessor architecture defined execute state;

executing said user task including establishing a user task procedure stack;

receiving an interrupt request of higher priority than the current processor interrupt level;

suspending said user task execution;

having interrupt record and frame containing user task context automatically stored in said task procedure stack, thereby preventing the microprocessor architecture defined switch to said interrupt stack;

storing volatile global registers in local registers, which are dedicated to the current interrupt frame;

setting said state bit to the inverse value of the microprocessor architecture defined interrupt state;

servicing said interrupt by operating out of said interrupt frame on said user procedure stack;

restoring volative global registers from local registers;

having said user task context, which includes the inverse value of said state bit, automatically restored from said task procedure stack; and

resuming execution of said interrupted user task.

2. The method of said "inside-out", inverse operation of claim 1 also including the following steps after said suspending said user task execution step:

determining if a preemption is necessary;

executing a user task of higher priority than the said user task which was interrupted when said preemption is determined, said higher priority task being executed from a task procedure stack;

maintaining said interrupted user task context on the said interrupted user task procedure stack; and

switching from said task procedure stack holding said higher priority user task to said interrupted task procedure stack.

3. A method of inverse operation of a multi-tasking priority interrupt capable microprocessor having a processor unit and memory space addressable therefrom, a processor control register and a register set in said processor unit, a processor control block, interrupt table, interrupt stack and at least one task procedure stack in said memory space, an interrupt controller connected to said processor unit, an operating system kernel connected to said processor unit, and an interrupt handler connected to said processor unit, said interrupt controller receiving interrupt signals from external sources, comprising the steps of:

receiving an interrupt request;

interrogating the priority level of said received interrupt request with respect to the current priority level;

suspending the current task in the presence of a higher priority interrupt request;

creating an interrupt record on said procedure stack and saving task context;

copying global registers to local registers;

setting the processor state to executing;

executing the interrupt handler function;

interrogating to determine for a higher priority task;

selecting a higher priority task in the presence of a higher priority task determination;

switching to a higher priority task procedure stack;

setting the processor state to interrupted;

executing the higher priority task;

switching to the interrupted task procedure stack;

restoring said global registers from local registers;

restoring task context from said interrupt record; and

resuming the suspended task.

4. The method of claim 3 wherein after the step of interrogating the priority level of said received interrupt request is the step of:

posting said interrupt request when it is of a lower priority and deferring the servicing of said interrupt request.

5. The method of claim 3 wherein after the step of interrogating to determine for a higher priority task, said step of restoring global registers is entered in the absence of higher priority task preemption determination.

6. A method of inverse operation of a mutli-tasking priority interrupt capable microprocessor having a processor unit and memory space addressable therefrom, a processor control register and a register set in said processor unit, a processor control block, interrupt table, interrupt stack and at least one task procedure stack in said memory space, an interrupt controller connected to said processor unit, an operating system kernel connected to said processor unit, and an interrupt handler connected to said processor unit, said interrupt controller receiving interrupt signals from external sources, comprising the steps of:

receiving an interrupt request of higher priority while an interrupt is being serviced;

suspending said interrupt handler function;

creating an interrupt record on said interrupt stack;

copying global registers to local registers;

executing higher priority interrupt handler function;

restoring said global registers from local registers;

restoring interrupt handler context from said interrupt record on said interrupt stack; and

resuming said interrupt handler function.