Transmission gate series multiplexer

• US 5,162,666 A
• Filed: 03/15/1991
• Issued: 11/10/1992
• Est. Priority Date: 03/15/1991
• Status: Expired due to Term

• Current Assignee: Ta-Wei Po, Translogic Technology Incorporated
• Original Assignee: Dzung J. Tran
• Inventors: Tran, Dzung J.
• Primary Examiner(s): Pascal, Robert J.
• Application Number:
  US07/670,075
• Time in Patent Office: 606 Days
• Field of Search: 307/243, 307/443, 307/448
• US Class Current: 327/408
• CPC Class Codes: H04J 3/047 Distributors with transistors or integrated circuits

Abstract

A multiplexer circuit is formed of two-to-one transmission gate multiplexer (TGM) circuits (80) connected in series. A first stage TGM (80) selects among two of the input variable signals (I0,I1). Each subsequent stage TGM (70) selects among the next preceding stage output signal (81) and another one of the input variable signals (I2). Each TGM is controlled by a unique control signal (S1,S2) so that loading on the control lines is limited to one TGM circuit to improve propagation delay. The series arrangement of TGM circuits can be extended as needed (M3,M4,M5).

Claims

1. A multiplexer circuit for selecting one of a plurality of input variable signals, comprising:

two or more TGM circuits coupled in series;

each TGM circuit including first and second transmission gates and having first and second input terminals, an output terminal and a control terminal;

the output terminal of a first one of the TGM circuits coupled to one of the input terminals of a second, adjacent one of the TGM circuits so as to propagate a selected one of the input signals through the first TGM circuit to said one input terminal of the second TGM circuit as an input signal; and

the other one of the second TGM input terminals coupled to receive one of the input signals, so that each successive TGM circuit in the series selects between the output of a next preceding TGM circuit and one of the input signals.

2. The multiplexer circuit according to claim 1 wherein each TGM circuit comprises a pair of transmission gates.

3. A multiplexer circuit according to claim 2 wherein each transmission gate comprises a pass transistor.

4. A multiplexer circuit according to claim 2 wherein each transmission gate comprises a complementary pair of transistors.

5. A multiplexer circuit according to claim 1 including a buffer circuit coupled to at least one of the TGM input terminals.

6. A multiplexer circuit according to claim 1 wherein at least one of the TGM circuits includes a pair of transmission gates and the control terminal of said one TGM circuit is coupled directly to a first one of the pair of transmission gates and is coupled through an inverter to the other transmission gate for controlling the pair of transmission gates in a complementary manner.

7. A multiplexer circuit for selecting one of a plurality of input variable signals comprising:

two or more TGM circuits coupled in series;

each TGM circuit including first and second transmission gates and having first and second input terminals, an output terminal and a control terminal;

the output terminal of a first one of the TGM circuits coupled to one of the input terminals of a second, adjacent one of the TGM circuits;

the other one of the second TGM input terminals coupled to receive one of the input variable signals, whereby each TGM circuit selects one of the output of a next preceding TGM circuit and one of the input variable signals; and

wherein each TGM control terminal is coupled to receive a unique control signal.

8. A multiplexer circuit according to claim 7 wherein each TGM circuit comprises a pair of transmission gates.

9. A multiplexer circuit according to claim 8 wherein each transmission gate comprises a pair of pass transistors.

10. A multiplexer circuit according to claim 8 wherein each transmission gate comprises a complementary pair of transistors.

11. A multiplexer circuit according to claim 7 including a buffer circuit coupled to at least one of the TGM input terminals.

12. A multiplexer circuit for selecting one of N input variable signals as a final output signal, where N is an integer greater than or equal to three, responsive to the states of N-1 binary control signals, comprising:

N-1 transmission gate multiplexer (TGM) circuits, each TGM circuit including a pair of signal input terminals, a control terminal and an output terminal;

each control terminal coupled to receive a respective one of the binary control signals;

each first input terminal except the first stage first input terminal coupled to the output terminal of a next adjacent stage;

each second input terminal coupled to receive a respective one of the input variables; and

the input stage first input terminal coupled to receive a first one of the input variables, whereby the final stage output terminal provides a selected one of the input variable signals as the final output signal.

13. A multiplexer circuit according to claim 12 including a buffer circuit coupled to at least one of the TGM input terminals.

14. A multiplexer circuit according to claim 12 wherein at least one of the TGM circuits includes a pair of transmission gates and the control terminal of said one TGM circuit is coupled directly to a first one of the pair of transmission gates and is coupled through an inverter to the other transmission gate for controlling the pair of transmission gates in a complementary manner.

15. A multiplexer circuit comprising:

a first stage TGM circuit having first and second signal input terminals, a control input terminal and an output terminal;

the first and second signal input terminals coupled to receive first and second input variables, respectively;

the control input coupled to receive a first control signal;

a second stage TGM circuit having first and second signal input terminals, a control input terminal and an output terminal;

one of the second stage signal input terminals coupled to the first stage output terminal;

the other one of the second stage signal input terminals coupled to receive a third input variable; and

the second stage control input terminal coupled to receive a second control signal;

whereby the circuit forms a three-to-one multiplexer.

16. A multiplexer circuit according to claim 15 further comprising:

a third stage TGM circuit having first and second signal input terminals, a control input terminal and an output terminal;

one of the third stage signal input terminals coupled to the second stage output terminal;

the other one of the third stage signal input terminals coupled to receive a fourth input variable; and

the third stage control input terminal coupled to receive a third control signal;

whereby the circuit forms a 4;

1 multiplexer.

17. A multiplexer circuit according to claim 16 further comprising:

a fourth stage TGM circuit having first and second signal input terminals, a control input terminal and an output terminal;

one of the fourth stage signal input terminals coupled to the third stage output terminal;

the other one of the fourth stage signal input terminals coupled to receive a fifth input variable; and

the fourth stage control input terminal coupled to receive a fourth control signal;

whereby the circuit forms a 5;

1 multiplexer.

18. A multiplexer circuit according to claim 15 including a buffer circuit coupled to at least one of the TGM input terminals.

19. A method of selecting one of a plurality N of input variable signals as a final output signal, comprising the steps of:

providing N-1 two-to-one transmission gate multiplexer (TGM) circuits coupled in series;

in a first one of the TGM circuits, selecting one of first and second input variable signals as the first TGM output signal;

in each subsequent TGM circuit, selecting one of the next preceding TGM output signal and a respective one of the input variable signals as the TGM output signal; and

in a final one of the TGM circuits, selecting one of the next preceding TGM output signal and a final one of the input variable signals as the final output signal.

20. A method according to claim 19 further comprising providing N-1 control signals and controlling each of the TGM circuits with a respective one of the control signals, thereby limiting the loading on each of the control signals to one TGM circuit.

21. A multiplexer circuit for selecting one of a plurality of input signals, comprising:

two or more 2;

1 multiplexer circuits coupled in series, each multiplexer circuit having first and second input terminals, an output terminal and a control terminal;

the output terminal of a first one of the multiplexer circuits coupled to one of the input terminals of a second, adjacent one of the multiplexer circuits so as to propagate a selected one of the input signals through the first multiplexer circuit to said one input terminal of the second multiplexer circuit as an input signal; and

the other one of the second multiplexer input terminals coupled to receive one of the input signals, so that each successive multiplexer circuit in the series selects between the output of a next preceding multiplexer circuit and one of the input signals.

22. A multiplexer circuit for selecting one of a plurality of input signals comprising:

two or more multiplexer circuits coupled in series;

each multiplexer circuit having first and second input terminals, an output terminal and a control terminal;

the output terminal of a first one of the multiplexer circuits coupled to one of the input terminals of a second, adjacent one of the multiplexer circuits;

the other one of the second multiplexer input terminals coupled to receive one of the input variable signals, whereby each multiplexer circuit selects one of the output of a next preceding multiplexer circuit and one of the input variable signals; and

each multiplexer control terminal being coupled to receive a unique control signal.

23. A multiplexer circuit for selecting one of N input variable signals as a final output signal, where N is an integer greater than or equal to three, responsive to the states of N-1 binary control signals, comprising:

N-1 two-to-one 2;

1 multiplexer circuits, each multiplexer circuit including a pair of input terminals, a control terminal and an output terminal;

each control terminal coupled to receive a respective one of the binary control signals;

each first input terminal except a first multiplexer first input terminal coupled to the output terminal of a next adjacent multiplexer;

each second input terminal coupled to receive a respective one of the input variables; and

the first multiplexer first input terminal coupled to receive a first one of the input variables, whereby the final multiplexer output terminal provides a selected one of the input variable signals as the final output signal.

24. A multiplexer circuit comprising:

a first stage multiplexer circuit having first and second signal input terminals, a control input terminal and an output terminal;

the first and second signal input terminals coupled to receive first and second input variables, respectively;

the control input coupled to receive a first control signal;

a second stage multiplexer circuit having first and second signal input terminals, a control input terminal and an output terminal;

one of the second stage signal input terminals coupled to the first stage output terminal;

the other one of the second stage signal input terminals coupled to receive a third input variable; and

the second stage control input terminal coupled to receive a second control signal;

whereby the circuit forms a three-to-one multiplexer.

25. A multiplexer circuit according to claim 24 further comprising:

a third stage multiplexer circuit having first and second signal input terminals, a control input terminal and an output terminal;

one of the third stage signal input terminals coupled to the second stage output terminal;

the other one of the third stage signal input terminals coupled to receive a fourth input variable; and

the third stage control input terminal coupled to receive a third control signal;

whereby the circuit forms a 4;

1 multiplexer.

26. A multiplexer circuit according to claim 25 further comprising:

a fourth stage multiplexer circuit having first and second signal input terminals, a control input terminal and an output terminal;

one of the fourth stage signal input terminals coupled to the third stage output terminal;

the other one of the fourth stage signal input terminals coupled to receive a fifth input variable; and

the fourth stage control input terminal coupled to receive a fourth control signal;

whereby the circuit forms a 5;

1 multiplexer.

27. A method for selecting one of a plurality N of input variable signals as a final output signal, comprising the steps of:

providing N-1 two-to-one multiplexer circuits coupled in series;

in a first one of the multiplexer circuits, selecting one of first and second input variable signals as the first multiplexer output signal;

in each subsequent multiplexer circuit, selecting one of the next preceding multiplexer output signal and a respective one of the input variable signals as the multiplexer output signal; and

in a final one of the multiplexer circuits, selecting one of the next preceding multiplexer output signal and a final one of the input variable signals as the final output signal.