Current-steering CMOS logic family

• US 5,162,674 A
• Filed: 05/10/1991
• Issued: 11/10/1992
• Est. Priority Date: 05/10/1991
• Status: Expired due to Term

• Current Assignee: Oregon State University (Oregon University System)
• Original Assignee: Oregon State University (Oregon University System)
• Inventors: Liang, Guojin, Allstot, David J., Yang, Howard C.
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): ROSEEN, RICHARD R
• Application Number:
  US07/698,672
• Time in Patent Office: 550 Days
• Field of Search: 364/600, 341/110, 307/443, 307/475, 307/451, 307/455, 307/450, 307/477, 307/459
• US Class Current: 326/115
• CPC Class Codes: H01L 27/0203 Particular design considerations for integrated circuits
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 17/6872 using complementary field-effect transistors
• CPC Class Codes: H03K 19/0948 using CMOS or complementary insulated gate field-effect transistors

Abstract

In integrated circuitry having both analog and digital circuits fabricated on the same substrate, switching transients produced by the digital circuitry can propagate through the substrate and induce deleterious effects in the associated analog circuitry. Such switching transients are greatly minimized by the disclosed family of CMOS logic circuits in which a constant DC bias current is steered to change logic states.

Claims

1. A mixed mode integrated circuit comprising:

a substrate;

one or more analog circuits fabricated on said substrate; and

one or more digital circuits fabricated on said substrate;

at least one of said digital circuits comprising;

a CMOS input transistor;

a CMOS output transistor;

first and second power lines;

a constant current source;

the sources of the input and output transistors being connected together and coupled to the second power line;

the gate of the input transistor being connected to a digital circuit input terminal;

the gate of the output transistor being connected to the drain of the input transistor;

the drain of the output transistor being connected to a digital circuit output terminal;

the drain of the output transistor being coupled to the first power line through the constant current source; and

the drain of the input transistor being connected to one of either the digital input terminal or the digital output terminal;

wherein switching currents from the digital circuits are prevented from generating large noise spikes.

2. The integrated circuit of claim 1 which further includes:

a second MOS transistor; and

a second digital circuit input terminal;

wherein;

the drain of the second transistor is connected to the drain of the first output transistor;

the source of the second transistor is connected to the source of the first output transistor; and

the gate of the second transistor is connected to the second digital circuit input terminal.

3. The integrated circuit of claim 2 in which the gates of the input and output transistors are connected together.

4. The integrated circuit of claim 3 in which a width-to-length ratio of the input transistor is different than that of the output transistor.

5. The integrated circuit of claim 4 in which the width-to-length ratio of the output transistor is approximately twice that of the input transistor.

6. The integrated circuit of claim 1 in which the gates of the input and output transistors are connected together.

7. The integrated circuit of claim 6 in which a width-to-length ratio of the input transistor is different than that of the output transistor.

8. The integrated circuit of claim 7 in which the width-to-length ratio of the output transistor is approximately twice that of the input transistor.

9. The integrated circuit of claim 2 in which the gate and drain of the output transistor are connected together.

10. The integrated circuit of claim 9 in which a width-to-length ratio of the output transistor is different than that of the input transistor.

11. The integrated circuit of claim 10 in which the width-to-length ratio of the input transistor is approximately twice that of the output transistor.

12. The integrated circuit of claim 1 in which the gate and drain of the output transistor are connected together.

13. The integrated circuit of claim 12 in which a width-to-length ratio of the output transistor is different than that of the input transistor.

14. The integrated circuit of claim 13 in which the width-to-length ratio of the input transistor is approximately twice that of the output transistor.

15. A MOS logic circuit featuring reduced switching currents, the circuit comprising:

a MOS input transistor;

a MOS output transistor;

first and second power lines;

a constant current source;

the sources of the input and output transistors being connected together and coupled to the second power line;

the gates of the input and output transistors being connected together and connected to the drain of the input transistor, the drain of the input transistor defining an input terminal; and

the drain of the output transistor being coupled to the first power line through the constant current source and defining an output terminal;

wherein switching currents are prevented from generating large noise spikes.

16. The logic circuit of claim 15 in which a width-to-length ratio of the output transistor is different than that of the input transistor.

17. The logic circuit of claim 15 which further includes:

a plurality N of MOS output transistors;

N constant current sources;

N output terminals;

the sources of the input transistor and of all of the output transistors being connected together and coupled to the second power line;

the gates of the input transistor and of all of the output transistors being connected together and connected to the drain of the input transistor;

the drain of each output transistor being coupled to the first power line through one of said N constant current sources and defining one of said N output terminals.

18. The logic circuit of claim 17 in which a width-to-length ratio of a plurality of the output transistors is different than that of the input transistor.

19. The logic circuit of claim 15 which further includes:

a second MOS input transistor;

a second MOS output transistor;

the sources of the second input and output transistors being connected together and connected to the sources of the first input and output transistors;

the gates of the second input and output transistors being connected together and connected to the drain of the second input transistor, the drain of the second input transistor defining a second input terminal;

the drain of the second output transistor being connected to the drain of the first output transistor.

20. A MOS logic circuit featuring reduced switching currents, the circuit comprising:

a MOS input transistor;

a MOS output transistor;

first and second power lines;

a constant current source;

the sources of the input and output transistors being connected together and coupled to the second power line;

the drains of the input and output transistors being connected together and to the gate of the output transistor and defining a voltage-mode output terminal, said connected drains being coupled to the first power line through the constant current source;

the gate of the input transistor defining a voltage mode input terminal;

wherein switching currents are prevented from generating large noise spikes.

21. The logic circuit of claim 20 in which a width-to-length ratio of the input transistor is different than that of the output transistor.

22. The logic circuit of claim 20 which further includes:

a second MOS input transistor;

the source of the second input transistor being connected to the source of the first input transistor;

the drain of the second input transistor being connected to the drain of the first input transistor;

the gate of the second input transistor defining a second voltage mode input terminal.