Functional at speed test system for integrated circuits on undiced wafers

• US 5,162,728 A
• Filed: 09/11/1990
• Issued: 11/10/1992
• Est. Priority Date: 09/11/1990
• Status: Expired due to Term

• Current Assignee: Medallion Technology, LLC
• Original Assignee: Cray Computer Corporation (Hewlett-Packard Enterprise Company)
• Inventors: Huppenthal, Jon
• Primary Examiner(s): NGUYEN, VINH P
• Application Number:
  US07/580,765
• Time in Patent Office: 791 Days
• Field of Search: 324/158 R, 324/158 F, 324/73.1, 324/72.5, 324/158 P, 437/8, 371/1, 371/15.1, 371/16.1, 371/27, 371/25.1, 439/482, 439/824, 361/397, 361/400, 361/401, 174/52.4, 174/52.2
• US Class Current: 324/756.03
• CPC Class Codes: G01R 31/316 Testing of analog circuits G01R31/2851 takes precedence

Abstract

A digital test system for functionally testing undiced ICs on wafers at relatively high test frequencies includes an improved probe card and interface assemblies. The probe card and interface assemblies each include a plurality of printed circuit boards laminated together as a single laminated structure. Equal length and equal impedance elongated micro strip test signal traces conduct the signals to and from a probe ring with a plurality of resilient probes physically and electrically in contact with the contact pads of the IC. Other circuit patterns includes a relatively large reference plane and a power plane of approximately equal size. The interface assembly performs selective I/O functions to electrically conduct input signals from a test signal generator to the probe card assembly and to electrically conduct response signals from the probe card assembly to the signal analyzer for determining the proper functionality of the IC. The printed circuit techniques assures a high degree of signal integrity, control over the signals at very high test frequencies, and efficiency in signal path routing.

Claims

1. In a digital test system for functionally testing undiced integrated circuits or dies on wafers at relatively high test frequencies, the system having generator means for generating input signals to be applied to a die under test or DUT and also having analyzer means for analyzing response signals supplied by the DUT in response to the input signals to thereby determine if the DUT is functioning properly, the DUT including a plurality of contact pads arranged in a predetermined configuration, an improvement in combination therewith comprising:

a probe card assembly including a plurality of printed circuit boards laminated together as a single laminated structure, a plurality of printed circuit patterns formed on the boards, a first one of the circuit patterns including a plurality of equal length and equal impedance elongated micro strip test signal traces, a second one of the circuit patterns including a relatively large reference plane which extends substantially over the test signal traces and is separated from the test signal traces by a uniform thickness of a circuit board to establish a uniform impedance per unit of length for the test signal traces, a third one of the circuit patterns including a power plane of a size approximately equal to the size or the reference plane, a probe ring having a plurality of resilient probes retained by a mounting ring in a pattern in which tips at one end of the probes are positioned to physically and electrically contact the contact pads of the DUT, the mounting ring attached to the laminated structure, an end of each of the probes opposite the tip electrically connected to the circuit patterns of the laminated structure, the connection end of a majority of the probes electrically connected to the ends of test signal traces, the connection end of each of a plurality of the remaining probes connected to at least one of the power plane and the reference plane, and a plurality of high frequency connectors attached to the laminated structure in electrical contact with the test signal traces at the end thereof opposite the end at which the connection ends are connected; and

interface means for electrically conducting the input signals from the generator means to the probe card assembly and for electrically conducting the response signals from the probe card assembly to the analyzer means, the interface means including a plurality of high frequency conductors electrically connected to the high frequency connectors of the probe card assembly for conducting the input and response signals to and from the DUT, respectively.

2. A system as defined in claim 1 further comprising a plurality of vias extending through the laminated structure by which to electrically interconnect the test signal traces and the connection ends of the probes, and wherein the third circuit pattern also includes a sensing conductor extending from the power plane at a sensing point approximately at the location where the vias connect the connection ends of the probes to the power plane.

3. A system as defined in claim 2 wherein the power plane includes a positive power plane and a negative power plane, the vias connect the connection ends of the remaining probes to one of either of the positive and negative power planes, and the third circuit pattern includes a positive and a negative sensing conductor extending from the positive and negative power planes, respectively, at sensing points approximately at the location where the vias connect the connection ends of the probes to the power planes.

4. A system as defined in claim 3 wherein the sensing points are located on the power planes at essentially the most remote location from the point at which the power planes are supplied with power.

5. A system as defined in claim 1 wherein the plurality of high frequency connectors include a first mating portion of the high frequency connector, the plurality of high frequency conductors of the interface means include a second mating portion of the high frequency connector, and the first and second mating portions of each high frequency connector connect by sliding on to one another.

6. A system as defined in claim 5 further comprising a bulkhead means for retaining the second mating portions of the high frequency connectors in a predetermined pattern corresponding to the pattern of the first mating portions of the high frequency connectors attached to the laminated structure, to allow both mating portions of all of the high frequency connectors to connect and separate simultaneously.

7. A system as defined in claim 1 wherein the probes are formed of beryllium copper.

8. A system as defined in claim 1 wherein the interface means comprises an interface card including a plurality of printed circuit boards laminated together as a single laminated structure, the printed circuit boards including printed circuit patterns formed thereon, and the printed circuit patterns include a micro strip portion which forms a portion of an interconnect conductor, the interconnect conductor defined by a portion of a high frequency conductor of the interface means which is electrically connected to the test signal traces of the probe card assembly.

13. A system as defined in claim 1 further comprising a plurality of vias extending through the laminated structure, and wherein the test signal traces and the connection ends of the probes are electrically interconnected at said vias to allow said vias to conduct the input and response signals to and from said probes, respectively.

9. In a digital test system for functionally testing undiced integrated circuits or dies on wafers at relatively high test frequencies, the system having generator means for generating input signals to be applied to a die under test or DUT and also having analyzer means for analyzing response signals supplied by the DUT in response to the input signals to thereby determine if the DUT is functioning properly, the DUT including a plurality of contact pads arranged in a predetermined configuration, an improvement in combination therewith comprising:

a probe card assembly including a plurality of printed circuit boards laminated together as a single laminated structure, a plurality of printed circuit patterns formed on the boards, a first one of the circuit patterns including a plurality of equal length and equal impedance elongated micro strip test signal traces, a second one of the circuit patterns including a relatively large reference plane which extends substantially over the test signal traces and is separated from the test signal traces by a uniform thickness of a circuit board to establish a uniform impedance per unit of length for the test signal traces, a third one of the circuit patterns including a power plane of a size approximately equal to the size of the reference plane, a probe ring having a plurality of resilient probes retained by a mounting ring in a pattern in which tips at one end of the probes are positioned to physically and electrically contact the contact pads of the DUT, the mounting ring attached to the laminated structure, an end of each of the probes opposite the tip electrically connected to the circuit patterns of the laminated structure, the connection end of a majority of the probes electrically connected to the ends of test signal traces, the connection ends of each of a plurality of the remaining probes connected to at least one of the power plane and the reference plane, and a plurality of high frequency conductors attached to the laminated structure in electrical contact with the test signal traces at the end thereof opposite the end at which the connection ends are connected; and

interface means for electrically conducting the input signals from the generator means to the probe card assembly and for electrically conducting the response signals from the probe card assembly to the analyzer means, the interface means including a plurality of high frequency conductors electrically connected to the high frequency connectors of the probe card assembly for conducting the input and response signals to and from the DUT, respectively; and

wherein;

the first circuit pattern includes a power divider means formed by micro strip traces, the power divider means receiving a test clock signal having a predetermined frequency from the interface means and in response thereto supplying a pair of DUT clock signals of approximately equal power.

10. A system as defined in claim 9 wherein the power divider means further adds a reflected signal of approximately equal amplitude to a primary signal derived by the power divider means to establish the power of each of the DUT clock signals at a level of approximately twice the power of the primary signal.

11. A system as defined in claim 9 wherein the first circuit pattern further includes a 180 degree phase delay means formed by a micro strip trace which is connected to receive one of the DUT clock signals and phase shift the one DUT clock signal by 180 degrees relative to the other DUT clock signal.

12. A system as defined in claim 11 wherein the power divider means comprises first and second micro strip branches which each have a length of one-fourth of the wavelength of the predetermined frequency of the test clock signal, the micro strip trace forming the phase delay means is connected to the terminal end of the second branch, and the two DUT clock signals form a true and a complement DUT clock signal which are respectively present at the terminal end of the first branch and at the terminal end of the micro strip trace forming the phase delay means.

14. In a digital test system for functionally testing undiced integrated circuits or dies on wafers at relatively high test frequencies, the system having generator means for generating input signals to be applied to a die under test or DUT and also having analyzer means for analyzing response signals supplied by the DUT in response to the input signals to thereby determine if the DUT is functioning properly, the DUT including a plurality of contact pads arranged in a predetermined configuration, an improvement in combination therewith comprising:

a probe card assembly including a plurality of printed circuit boards laminated together as a single laminated structure, a plurality of printed circuit patterns formed on the boards, a first one of the circuit patterns including a plurality of equal length and equal impedance elongated micro strip test signal traces, a second one of the circuit patterns including a relatively large reference plane which extends substantially over the test signal traces and is separated from the test signal traces by a uniform thickness of a circuit board to establish a uniform impedance per unit of length for the test signal traces, a third one of the circuit patterns including a power plane of a size approximately equal to the size of the reference plane, a probe ring having a plurality of resilient probes retained by a mounting ring in a pattern in which tips at one end of the probes are positioned to physically and electrically contact the contact pads of the DUT, the mounting ring attached to the laminated structure, an end of each of the probes opposite the tip electrically connected to the circuit patterns of the laminated structure, the connection end of a majority of the probes electrically connected to the ends of test signal traces, the connection end of each of a plurality of the remaining probes connected to at least one of the power plane and the reference plane, and a plurality of high frequency connectors attached to the laminated structure in electrical contact with the test signal traces at the end thereof opposite the end at which the connection ends are connected; and

interface means for electrically conducting the input signals from the generator means to the probe card assembly and for electrically conducting the response signals from the probe card assembly to the analyzer means, the interface means including a plurality of high frequency conductors electrically connected to the high frequency connectors of the probe card assembly for conducting the input and response signals to and from the DUT, respectively; and

wherein;

the high frequency conductors of the interface means include interconnect conductors electrically connected to the high frequency connectors connected to the test signal traces of the probe card assembly, and the interface means comprises a plurality of selection switch means by which to selectively alternatively connect each interconnect conductor to either receive the input signal from the generator means or to transmit the response signal to the analyzer means.

15. A system as defined in claim 14 wherein the selection switch means includes a terminal at which the input signal from the generator means is received, and further comprises a terminating impedance means for maintaining the strength of the input signal at said selection switch means.

16. A system as defined in claim 14 further comprising computer means for operatively controlling the operation of the generator means and the analyzer means by delivering control signals, and wherein the interface means further comprises switch control means receptive of a control signal from the computer means and operative in response thereto for signalling the selection switch means to change the state of its selective alternative connection.

17. A system as defined in claim 16 wherein the selection switch means comprises a GaAs switch, the switch control means comprises a comparator, and the interface means comprises an interface card including a plurality of printed circuit boards laminated together as a single laminated structure, the printed circuit boards including printed circuit patterns formed thereon, and the printed circuit patterns define the selection switch means, the control switch means, the impedance means and the interconnect conductor.

18. In a digital test system for functionally testing undiced integrated circuits or dies on wafers at relatively high test frequencies, the system having generator means for generating input signals to be applied to a die under test or DUT and also having analyzer means for analyzing response signals supplied by the DUT in response to the input signals to thereby determine if the DUT is functioning properly, the DUT including a plurality of contact pads arranged in a predetermined configuration, an improvement in combination therewith comprising:

a probe card assembly including a plurality of printed circuit boards laminated together as a single laminated structure, a plurality of printed circuit patterns formed on the boards, a first one of the circuit patterns including a plurality of equal length and equal impedance elongated micro strip test signal traces, a second one of the circuit patterns including a relatively large reference plane which extends substantially over the test signal traces and is separated from the test signal traces by a uniform thickness of a circuit board to establish a uniform impedance per unit of length for the test signal traces, a third one of the circuit patterns including a power plane of a size approximately equal to the size of the reference plane, a probe ring having a plurality of resilient probes retained by a mounting ring in a pattern in which tips at one end of the probes are positioned to physically and electrically contact the contact pads of the DUT, the mounting ring attached to the laminated structure, an end of each of the probes opposite the tip electrically connected to the circuit patterns of the laminated structure, the connection end of a majority of the probes electrically connected to the ends of test signal traces, the connection end of each of a plurality of the remaining probes connected to at least one of the power plane and the reference plane, and a plurality of high frequency connectors attached to the laminated structure in electrical contact with the test signal traces at the end thereof opposite the end at which the connection ends are connected;

clock means for generating a system clock signal at a predetermined frequency; and

interface means for electrically conducting the input signals from the generator means to the probe card assembly and for electrically conducting the response signals from the probe card assembly to the analyzer means, the interface means further connected to the clock means and receptive of the system clock signal;

the interface means including a plurality of high frequency conductors electrically connected to the high frequency conductors of the probe card assembly for conducting the input and response signals to and from the DUT, respectively, directional coupler means for generating a coupled signal at the frequency of the system clock signal, and divider means receptive of the coupled signal and operative in response thereto for deriving a clock signal having a frequency which is an integer division of the frequency of the system clock signal, the interface means further electrically conducting the clock signal to the generator and analyzer means to synchronize operation of the generator means and the analyzer means.

19. A system as defined in claim 18 further comprising bias means for adding a DC bias level signal to the coupled signal prior to receipt thereof by the divider means, and wherein the divider means comprises a flip flop.

20. A system as defined in claim 19 wherein the interface means comprises an interface card including a plurality of printed circuit boards laminated together as a single laminated structure, the printed circuit boards including printed circuit patterns formed thereon, and the printed circuit patterns include a micro strip portion which forms the directional coupler means, another portion which forms the divider means, another micro strip portion which supplies the system clock signal to the probe card assembly, and a further micro strip portion which conducts the clock signal which is received by the generator means and the analyzer means.

21. A method of functionally testing undiced integrated circuits or dies on wafers at relatively high test frequencies using a digital test system having a generator for generating input signals to be applied to a die under test or DUT and also having an analyzer for analyzing response signals supplied by the DUT in response to the input signals to thereby determine if the DUT is functioning properly, the DUT including a plurality of contact pads arranged in a predetermined configuration, said method comprising the steps of:

physically and electrically contacting the contact pads of the DUT with a plurality of resilient probes retained in a pattern in which tips at one end of the probes are positioned to align with the contact pads;

laminating a plurality of printed circuit boards together as a single laminated structure in which a plurality of printed circuit patterns are formed on the boards;

forming a plurality of equal length and equal impedance elongated micro strip test signal traces on a first one of the circuit patterns;

forming a reference plane which extends substantially over the test signal traces and is separated from the test signal traces by a uniform thickness of a circuit board to establish a uniform impedance per unit of length for the test signal traces on a second one of the circuit patterns, the reference plane being relatively larger than the test signal traces;

forming a power plane of a size approximately equal to the size of the reference plane on a third one of the circuit patterns;

electrically connecting each of the probes at a connection end opposite the tip to the circuit patterns of the laminated structure, with a majority of the probes electrically connected to the ends of the test signal traces, and with a plurality of the remaining probes connected to at least one of the power plane and the reference plane;

attaching a plurality of high frequency conductors to the laminated structure in electrical contact with the test signal traces at the end thereof opposite the end at which the connection ends of the probes are connected;

electrically conducting input signals from the generator through the high frequency conductors to the test signal traces; and

electrically conducting the response signals from the DUT to the analyzer through the high frequency conductors.

22. A method as defined in claim 21 further comprising:

extending a plurality of vias through the laminated structure to electrically interconnect the test signal traces and the connection ends of the majority of the probes and to electrically interconnect the plurality of remaining probes at the connection ends to the power plane and reference plane; and

including a sensing conductor in the third circuit pattern, the sensing conductor extending from the power plane at a sensing point located approximately where the vias connect the connection ends of the probes to the power plane.

23. A method as defined in claim 22 further comprising:

supplying the power plane with power; and

locating the sensing point on the power plane at essentially the most remote location from the point at which the power plane is supplied with power.

24. A method as defined in claim 21 further comprising:

attaching a first mating portion of each of the plurality of high frequency conductors to the laminated structure in electrical contact with the test signal traces at the end thereof opposite the end at which the connection ends are connected;

attaching a second mating portion of each of the plurality of high frequency conductors to a bulkhead in a predetermined pattern corresponding to the pattern of the first mating portions connected to the laminated structure, to allow both mating portions connectors to connect and separate simultaneously by sliding onto and off of each other, respectively.

25. A method as defined in claim 21 further comprising:

extending a plurality of vias through the laminated structure to electrically connect with the connection ends of the probes; and

sensing the signals from said probes at the vias.

26. A method as defined in claim 21 further comprising:

forming a portion of each high frequency conductor as an interconnect conductor;

connecting each interconnect conductor to a test signal trace;

selectively alternatively connecting said interconnect conductor to either receive the input signal from the generator or to transmit the response signal to the analyzer.

27. A method as defined in claim 26 further comprising:

utilizing a plurality of selection switches by which to selectively alternatively connect each interconnect conductor;

operatively controlling the operation of the generator and the analyzer by delivering control signals thereto; and

operatively controlling the selection switch to change the state of its selective alternative connection by delivering control signals thereto.

28. A method of functionally testing undiced integrated circuits or dies on wafers at relatively high test frequencies using a digital test system having a generator for generating input signals to be applied to a die under test or DUT and also having an analyzer for analyzing response signals supplied by the DUT in response to the input signals to thereby determine if the DUT is functioning properly, the DUT including a plurality of contact pads arranged in a predetermined configuration, said method comprising the steps of:

physically and electrically contacting the contact pads of the DUT with a plurality of resilient probes retained in a pattern in which tips at one end of the probes are positioned to align with the contact pads;

laminating a plurality of printed circuit boards together as a single laminated structure in which a plurality of printed circuit patterns are formed on the boards;

forming a plurality of equal length and equal impedance elongated micro strip test signal traces on a first one of the circuit patterns;

forming a power divider on the first circuit pattern using micro strip traces;

forming a reference plane which extends substantially over the test signal traces and is separated from the test signal traces by a uniform thickness of a circuit board to establish a uniform impedance per unit of length for the test signal traces on a second one of the circuit patterns, the reference plane being relatively larger than the test signal traces;

forming a power plane of a size approximately equal to the size of the reference plane on a third one of the circuit patterns;

electrically connecting each of the probes at a connection end opposite the tip to the circuit patterns of the laminated structure, with a majority of the probes electrically connected to the ends of the test signal traces, and with a plurality of the remaining probes connected to at least one of the power plane and the reference plane;

attaching a plurality of high frequency conductors to the laminated structure in electrical contact with the test signal traces at the end thereof opposite the end at which the connection ends of the probes are connected;

electrically conducting input signals from the generator through the high frequency conductors to the test signal traces;

supplying a test clock signal having a predetermined frequency to the power divider;

supplying a pair of DUT clock signals of approximately equal power by operation of the power divider in response to the test clock signal; and

electrically conducting the response signals from the DUT to the analyzer through the high frequency conductors.

29. A method as defined in claim 28 further comprising:

obtaining a primary signal component of each DUT clock signal by operation of the power divider in response to the test clock signal;

obtaining a reflected signal component of each DUT clock signal of approximately equal amplitude to the primary signal component by reflection of the primary signal component during operation of the power divider;

adding the reflected signal component to the primary signal component to establish the power of each of the DUT clock signals at a level of approximately twice the power of the primary signal component.

30. A method as defined in claim 29 further comprising:

forming a 180 degree phase delay using a micro strip trace;

connecting the phase delay to receive a DUT clock signal;

phase shifting the DUT clock signal conducted through the phase delay by 180 degrees to establish one DUT signal.

31. A method as defined in claim 30 further comprising:

forming first and second micro strip branches on the power divider which each have a length of one-fourth of the wavelength of the predetermined frequency of the test clock signal;

connecting the micro strip trace forming the phase delay to the terminal end of the second branch; and

supplying a true DUT clock signal and a complement DUT clock signal at the terminal end of the first branch and at the terminal end of the micro strip trace forming the phase delay, respectively.

32. A method of functionally testing undiced integrated circuits or dies on wafers at relatively high test frequencies using a digital test system having a generator for generating input signals to be applied to a die under test or DUT and also having an analyzer for analyzing response signals supplied by the DUT in response to the input signals to thereby determine if the DUT is functioning properly, the DUT including a plurality of contact pads arranged in a predetermined configuration, said method comprising the steps of:

physically and electrically contacting the contact pads of the DUT with a plurality of resilient probes retained in a pattern in which tips at one end of the probes are positioned to align with the contact pads;

laminating a plurality of printed circuit boards together as a single laminated structure in which a plurality of printed circuit patterns are formed on the boards;

forming a plurality of equal length and equal impedance elongated micro strip test signals traces on a first one of the circuit patterns;

forming a reference plane which extends substantially over the test signal traces and is separated from the test signal traces by a uniform thickness of a circuit board to establish a uniform impedance per unit of length for the test signal traces on a second one of the circuit patterns, the reference plane being relatively larger than the test signal traces;

forming a power plane of a size approximately equal to the size of the reference plane on a third one of the circuit patterns;

electrically connecting each of the probes at a connection end opposite the tip to the circuit patterns of the laminated structure, with a majority of the probes electrically connected to the ends of the test signal traces, and with a plurality of the remaining probes connected to at least one of the power plane and the reference plane;

attaching a plurality of high frequency conductors to the laminated structure in electrical contact with the test signal traces at the end thereof opposite the end at which the connection ends of the probes are connected;

generating a system clock signal at a predetermined frequency;

utilizing a directional coupler for generating an coupled signal at the frequency of the system clock signal;

supplying the coupled signal to a divider;

deriving a clock signal from the divider in response to the coupled signal, the clock signal having a frequency which is an integer division of the frequency of the system clock signal;

synchronizing the operation of the generator and analyzer by supplying the clock signal thereto;

electrically conducting input signals from the generator through the high frequency conductors to the test signal traces; and

electrically conducting the response signals from the DUT to the analyzer through the high frequency conductors.

33. In a digital test system for functionally testing undiced integrated circuits or dies on wafers at relatively high test frequencies, the system having generator means for generating input signals to be applied to a die under test or DUT and also having analyzer means for analyzing response signals supplied by the DUT in response to the input signals to thereby determine of the DUT is functioning properly, the DUT including a plurality of contact pads arranged in a predetermined configuration, an improvement in combination therewith comprising:

a probe card assembly including a plurality of printed circuit boards laminated together as a single laminated structure, a plurality of printed circuit patterns formed on the boards, a first one of the circuit patterns including a plurality of equal length and equal impedance elongated micro strip test signal traces, a second one of the circuit patterns including a relatively large reference plane which extends substantially over the test signal traces and is separated from the test signal traces by a uniform thickness of a circuit board to establish a uniform impedance per unit of length for the test signal traces, a third one of the circuit patterns including a positive power plane and a negative power plane which have a combined size approximately equal to the size of the reference plane, a probe ring having a plurality of resilient probes retained by a mounting ring in a pattern in which tips at one end of the probes are positioned to physically and electrically contact the contact pads of the DUT, the mounting ring attached to the laminated structure, an end of each of the probes opposite the tip electrically connected to the circuit patterns of the laminated structure, the connection end of a majority of the probes electrically connected to the ends of test signal traces, the connection end of each of a plurality of the remaining probes connected to one of the positive power plane, the negative power plane or the reference plane, the third circuit pattern also including a positive sensing conductor and a negative sensing conductor respectively extending from the positive and negative power planes at sensing points approximately at the location where the connection ends of the remaining probes connect to the power planes, and a plurality of high frequency connectors attached to the laminated structure in electrical contact with the test signal traces at the end thereof opposite the end at which the connection ends are connected; and

integrated means for electrically conducting the input signals from the generator means to the probe card assembly and for electrically conducting the response signals from the probe card assembly to the analyzer means, the interface means including a plurality of high frequency conductors electrically connected to the high frequency connectors of the probe card assembly for conducting the input and response signals to and from the DUT, respectively.

34. A system as defined in claim 33 wherein the sensing points are located on the power planes at essentially the most remote location from the point at which the power planes are supplied with power.

35. A method of functionally testing undiced integrated circuits or dies on wafers at relatively high test frequencies using a digital test system having a generator for generating input signals to be applied to a die under test or DUT and also having an analyzer for analyzing response signals supplied by the DUT in response to the input signals to thereby determine if the DUT is functioning properly, the DUT including a plurality of contact pads arranged in a predetermined configuration, said method comprising the steps of:

physically and electrically contacting the contact pads of the DUT with a plurality of resilient probes retained in a pattern in which tips at one end of the probes are positioned to align with the contact pads;

laminating a plurality of printed circuit boards together as a single laminated structure in which a plurality of printed circuit patterns are formed on the boards;

forming a plurality of equal length and equal impedance elongated micro strip test signal traces on a first one of the circuit patterns;

forming a reference plane which extends substantially over the test signal traces and is separated from the test signal traces by a uniform thickness of a circuit board to establish a uniform impedance per unit of length for the test signal traces on a second one of the circuit patterns, the reference plane being relatively larger than the test signal traces;

forming a power plane of a size approximately equal to the size of the reference plane on a third one of the circuit patterns;

electrically connecting each of the probes at a connection end opposite the tip to the circuit patterns of the laminated structure, with a majority of the probes electrically connected to the ends of the test signal traces, and with a plurality of remaining probes connected to at least one of the power plane and the reference plane;

supplying electrical power to the power plane at a power supply location;

including a sensing conductor in the third circuit pattern, the sensing conductor extending from the power plane at a sensing point located approximately where the connection ends of the probes are connected to the power plane, the sensing point located on the power plane at essentially the most remote location from the power supply location;

attaching a plurality of high frequency conductors to the laminated structure in electrical contact with the test signal traces at the end thereof opposite the end at which the connection ends of the probes are connected;

electrically conducting input signals from the generator through the high frequency conductors to the test signal traces; and

electrically conducting the response signals from the DUT to the analyzer through the high frequency conductors.

36. A method of functionally testing undiced integrated circuits or dies on wafers at relatively high test frequencies using a digital test system having a generator for generating input signals to be applied to a die under test or DUT and also having an analyzer for analyzing response signals supplied by the DUT in response to the input signals to thereby determine if the DUT is functioning properly, the DUT including a plurality of contact pads arranged in a predetermined configuration, said method comprising the steps of:

physically and electrically contacting the contact pads of the DUT with a plurality of resilient probes retained in a pattern in which tips at one end of the probes are positioned to align with the contact pads;

laminating a plurality of printed circuit boards together as a single laminated structure in which a plurality of printed circuit patterns are formed on the boards;

forming a plurality of equal length and equal impedance elongated micro strip test signal traces on a first one of the circuit patterns;

forming a reference plane which extends substantially over the test signal traces and is separated from the test signal traces by a uniform thickness of a circuit board to establish a uniform impedance per unit of length for the test signal traces on a second one of the circuit patterns, the reference plane being relatively larger than the test signal traces;

forming a power plane of a size approximately equal to the size of the reference plane on a third one of the circuit patterns;

electrically connecting each of the probes at a connection end opposite the tip to the circuit patterns of the laminated structure, with a majority of the probes electrically connected to the ends of the test signal traces, and with a plurality of the remaining probes connected to at least one of the power plane and the reference plane;

attaching a plurality of high frequency conductors to the laminated structure in electrical contact with the test signal traces at the end thereof opposite the end at which the connection ends of the probes are connected;

selectively alternatively connecting each of a plurality of high frequency conductors to either receive an input signal from the generator or to transmit a response signal to the analyzer;

utilizing a plurality of selection switches by which to selectively alternatively connect each of the plurality of high frequency conductors;

operatively controlling the operation of the generator and the analyzer by delivering control signals thereto;

operatively controlling the selection switch to change the state of its selective alternative connection by delivering control signals thereto;

electrically conducting the input signals to the DUT from the generator through the ones of the plurality of high frequency conductors connected to receive the input signal from the generator; and

electrically conducting the response signals to the analyzer from the DUT through the ones of the plurality of high frequency conductors connected to transmit the response signal to the analyzer.