Diffusionless conductor/oxide semiconductor field effect transistor and methods for making and using the same
First Claim
1. A source/drain diffusionless field effect transistor formed at the face of a semiconductor layer of a first conductivity type, comprising:
- a thin insulator layer overlying said semiconductor layer;
a source conductor formed on said thin insulator layer overlie a source inversion region of said semiconductor layer;
a drain conductor formed on said thin insulator layer to overlie a drain inversion region of said semiconductor layer and spaced from said first conductor, a channel region of said semiconductor layer defined between said source inversion region and said drain inversion region and further bounded by thick field oxide regions;
a control gate conductor overlying said channel region; and
at least one voltage source coupled to said drain conductor and said source conductor for inverting said source and drain inversion regions to a second conductivity type opposite said first conductivity type.
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Accused Products
Abstract
A diffusionless field effect transistor is formed at a face of a semiconductor layer (12) of a first conductivity type and includes a source conductor (36), a drain conductor (38) and a channel region (44). Source conductor (36) and drain conductor (38) are disposed to create inversion regions, and a second conductivity type opposite said first conductivity type, in the underlying source inversion region (40) and drain inversion region (42) of semiconductor layer (12) upon application of voltage. The transistor has a gate (54) insulatively overlying the channel region (44) to control the conductivity thereof.
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Citations
19 Claims
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1. A source/drain diffusionless field effect transistor formed at the face of a semiconductor layer of a first conductivity type, comprising:
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a thin insulator layer overlying said semiconductor layer; a source conductor formed on said thin insulator layer overlie a source inversion region of said semiconductor layer; a drain conductor formed on said thin insulator layer to overlie a drain inversion region of said semiconductor layer and spaced from said first conductor, a channel region of said semiconductor layer defined between said source inversion region and said drain inversion region and further bounded by thick field oxide regions; a control gate conductor overlying said channel region; and at least one voltage source coupled to said drain conductor and said source conductor for inverting said source and drain inversion regions to a second conductivity type opposite said first conductivity type. - View Dependent Claims (2, 3, 4, 5, 6, 12, 13, 14, 15)
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7. An array of diffusionless field-effect transistors formed at a face of a semiconductor layer of a first conductivity type, comprising:
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a thin insulator layer overlying said layer of semiconductor; a plurality of parallel, elongated drain conductors formed overlying said thin insulator layer; for each pair of drain conductors, an elongated source conductor formed in between and substantially parallel thereto, each source conductor spaced from adjacent ones of said drain conductors by a plurality of channel regions, said channel regions having thick field oxide areas formed between channel regions of adjacent transistors; and a plurality of elongated gate conductors formed at an angle to insulatively intersect said source conductors and said drain conductors, said gate conductors insulatively disposed adjacent said channel regions, field effect transistors formed at least some intersections of said gate conductors with said source conductors, drain conductors and channel regions. - View Dependent Claims (8)
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9. An array of memory cells comprising source/drain diffisionless field effect transistors formed at a face of a semiconductor layer of a first conductivity type, comprising:
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a plurality of parallel, elongated drain conductors formed at said face; for each pair of drain conductors, an elongated source conductor formed in between and in parallel thereto, said source conductors and said drain conductors spaced by a plurality of channel regions, to form memory cells with a cell associated with each channel region; a plurality of rows of said cells formed at an angle to said source conductors and said drain conductors, a control gate conductor for each said row insulatively disposed adjacent said channel regions in said row and insulated from said source and drain conductors, so as to control the conductance of said channel regions; and a plurality of thick field oxide areas formed in the channel regions between adjacent ones of said rows to electrically isolate cells. - View Dependent Claims (10, 11, 16, 17, 18, 19)
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Specification