Multi-state EEprom read and write circuits and techniques

• US 5,163,021 A
• Filed: 07/22/1991
• Issued: 11/10/1992
• Est. Priority Date: 04/13/1989
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SunDisk Corporation (Seagate Technology Holdings Plc)
• Inventors: Harari, Eliyahou, Lee, Winston, Mehrotra, Sanjay
• Primary Examiner(s): Bowler, Alyssa H.
• Application Number:
  US07/734,221
• Time in Patent Office: 477 Days
• Field of Search: 365/185, 365/104, 365/201, 365/207, 330/2, 330/257, 330/288
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3436 Arrangements for verifying correct programming or erasure
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2211/5631 Concurrent multilevel reading of more than one cell
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 2211/5645 Multilevel memory with current-mirror arrangements
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects

Abstract

Improvements in the circuits and techniques for read, write and erase of EEprom memory enable nonvolatile multi-state memory to operate with enhanced performance over an extended period of time. In the improved circuits for normal read, and read between write or erase for verification, the reading is made relative to a set of threshold levels as provided by a corresponding set of reference cells which closely track and make adjustment for the variations presented by the memory cells. In one embodiment, each Flash sector of memory cells has its own reference cells for reading the cells in the sector, and a set of reference cells also exists for the whole memory chip acting as a master reference. In another embodiment, the reading is made relative to a set of threshold levels simultaneously by means of a one-to-many current mirror circuit. In improved write or erase circuits, verification of the written or erased data is done in parallel on a group of memory cells at a time and a circuit selectively inhibits further write or erase to those cells which have been correctly verified. Other improvements includes programming the ground state after erase, independent and variable power supply for the control gate of EEprom memory cells.

Claims

1. A circuit for sensing a test current relative to a plurality of predetermined current levels, comprising:

a one-to-many current mirror means for reproducing a test current into one or more reproduced currents, said current mirror having a first leg for carrying the test current and a second leg comprising a plurality of branches, such that each branch is associated with a reference current level;

a first current source at each branch for reproducing a reproduced current therein, said reproduced current being substantially similar to the test current in the first leg;

a second current source at each branch for providing a reference current having one of the predetermined reference current levels; and

means for simultaneously detecting in each branch a relatively high or low voltage at a node between first and second current sources, the relatively high or low voltage corresponding to whether the reproduced current similar to the test current provided by the first current source has magnitude greater or less than that of the reference current provided by the second current source.

2. A circuit as in claim 1, wherein said test current is provided by a conduction current of a memory cell, said conduction current designating a memory state thereof.

3. A circuit as in claim 2, wherein said memory cell is an EEprom or a Flash EEprom.

4. A circuit as in claim 1, wherein said second current source in each branch is a programmable reference current source.

5. A circuit as in claim 4, wherein said test current is provided by a conduction current of a memory cell, said conduction current designating a memory state thereof.

6. A circuit as in claim 4, wherein said memory cell is an EEprom or a flash EEprom.

7. A circuit as in claim 4, wherein said programmable reference current source is provided by a conduction current of a memory cell, said conduction current having conduction current designating a memory state thereof.

8. A circuit as in claim 7, wherein said memory cell is an EEprom or a Flash EEprom.

9. A circuit as in claim 4, wherein said programmable reference current source is duplicated from an original programmable reference current source by a circuit which comprises:

first and second one-to-one current mirror means each having only one branch for each of its two legs, said first and second one-to-one current means being interconnected by one of their two legs, and said second current source being provided by connection to the other leg of the second one-to-one current mirror means; and

an original programmable reference current source for providing a reference current, said original programmable reference current source being connected to the other leg of the first one-to-one current mirror means, thereby mirroring substantially similar reference current into the interconnected leg, and in turn mirroring same into the other leg of the second one-to-one current means, thereby providing said second current source with substantially similar current as that of the original programmable reference current source.

10. A circuit as in claim 9, wherein said test current is provided by a conduction current of a memory cell designating a memory state thereof.

11. A circuit as in claim 10, wherein said memory cell is an EEprom or a Flash EEprom.

12. A circuit as in claim 9, wherein said programmable reference current source is provided by a memory cell having conduction current designating a memory state thereof.

13. A circuit as in claim 12, wherein said memory cell is an EEprom or a Flash EEprom.

14. A circuit as in claim 9, wherein the one-to-many current mirror means and the first one-to-one current mirror means comprise transistors having the same polarity, and the second one-to-one current mirror means comprise transistors having the opposite polarity.

15. A circuit as in claim 1, wherein said second current source for providing a predetermined reference current in each branch comprises:

a transistor of a predetermined size having a source, a drain and a gate; and

means for applying a predetermined reference voltage to the gate for producing one of the predetermined reference currents through the source and drain of the transistor of predetermined size;

said predetermined reference voltage being constant across the branches and said predetermined size differing across the branches so as to produce the plurality of predetermined reference currents among the branches.

16. A circuit as in claim 15, wherein said test current is provided by a conduction current of a memory cell, said conduction current designating a memory state thereof.

17. A circuit as in claim 16, wherein said memory cell is an EEprom or a Flash EEprom.

18. A circuit as in claim 15, wherein said constant reference current is provided by a conduction current of a memory cell, said conduction current designating a memory state thereof.

19. A circuit as in claim 18, wherein said memory cell is an EEprom or a Flash EEprom.

20. A circuit for sensing a test current relative to a plurality of predetermined reference current levels, each of the plurality of reference current levels being scalable by a multiplication factor from that of a lowest reference current level thereof, comprising:

a one-to-many current mirror means for reproducing a test current into one or more reproduced currents, said current mirror having a first leg for carrying the test current and a second leg comprising a plurality of branches, such that each branch is associated with a reference current level and a multiplication factor;

a first current source at each branch for reproducing a reproduced current therein, said reproduced current being scalable from the test current in the first leg by the associated multiplication factor;

a second current source at each branch for providing a highest reference current level from among said plurality of reference current levels; and

means for simultaneously detecting in each branch a relatively high or low voltage at a node between first and second current sources, the relatively high or low voltage corresponding to whether the reproduced current scaled from the test current provided by the first current source has magnitude greater or less than that of the highest reference current provided by the second current source.

21. A circuit as in claim 20, wherein said test current is provided by a conduction current of a memory cell, said conduction current designating a memory state thereof.

22. A circuit as in claim 21, wherein said memory cell is an EEprom or a Flash EEprom.

23. A circuit as in claim 20, wherein said highest reference current is provided by a conduction current of a memory cell, said conduction current designating a memory state thereof.

24. A circuit as in claim 23, wherein said memory cell is an EEprom or a Flash EEprom.

25. A circuit for sensing a test current relative to a plurality of predetermined reference current levels, each of the plurality of reference current levels being scalable by a multiplication factor from that of a given reference current level thereof, comprising:

a one-to-many current mirror means for reproducing the given reference current level into one or more reproduced currents, said current mirror having a first leg for carrying the given reference current and a second leg comprising a plurality of branches, such that each branch is associated with a reference current level and a multiplication factor;

a first current source at each branch for reproducing a reproduced current therein, said reproduced current being scalable from the given reference current level in the first leg by the associated multiplication factor;

a second current source at each branch for providing the test current; and

means for simultaneously detecting in each branch a relatively high or low voltage at a node between first and second current sources, the relatively high or low voltage corresponding to whether the reproduced current scaled from the lowest reference current level provided by the first current source has magnitude greater or less than that of the test current provided by the second current source.

26. A circuit as in claim 25, wherein said test current is provided by a conduction current of a memory cell, said conduction current designating a memory state thereof.

27. A circuit as in claim 26, wherein said memory cell is an EEprom or a Flash EEprom.

28. A circuit as in claim 25, wherein said lowest reference current is provided by a conduction current of a memory cell, said conduction current designating a memory state thereof.

29. A circuit as in claim 28, wherein said memory cell is an EEprom or a Flash EEprom.

30. In an integrated circuit memory system having an array of a plurality of addressable semiconductor electrically erasable and programmable memory (EEprom) cells of the type having a source, a drain, a control gate, a floating gate capable of retaining a charge level programmed into it during use of the memory system resulting in a definite memory state having a corresponding threshold of conduction current relative to one or more predetermined threshold current levels used to demarcate memory states, and an erase electrode capable of removing charge from said floating gate, and said memory system including a reading system for determining the programmed state of an addressed cell, said reading system comprising:

one or more reference memory cells constituted from the array of EEprom cells that are each respectively programmed with a charge that corresponds to each of said one or more predetermined thresholds; and

means responsive to said one or more reference memory cells for comparing the threshold current level of an addressed cell with that of said one or more reference memory cells, thereby determining relative to which of said one or more predetermined threshold levels the addressed cell lies, whereby one or more bits of data stored in the addressed cell is readable therefrom; and

wherein said means for comparing the threshold current level further comprising;

a one-to-many current mirror means for reproducing the threshold current level of an addressed cell into one or more reproduced currents, said current mirror having a first leg for carrying the threshold current level of an addressed cell and a second leg comprising a plurality of branches, such that each branch is associated with one of said one or more predetermined threshold levels;

a first current source at each branch for reproducing a reproduced current therein, said reproduced current being substantially similar to the threshold current level in the first leg;

a second current source at each branch for providing a reference current having one of the predetermined threshold levels; and

means for simultaneously detecting in each branch a relatively high or low voltage at a node between first and second current sources, the relatively high or low voltage corresponding to whether the reproduced current similar to the threshold current level provided by the first current source has magnitude greater or less than that of one of the predetermined threshold levels provided by the second current source.