Video display system using memory with parallel and serial access employing serial shift registers selected by column address

• US 5,163,024 A
• Filed: 05/09/1990
• Issued: 11/10/1992
• Est. Priority Date: 12/30/1983
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Novak, Mark F., Guttag, Karl M., Pinkham, Raymond, Redwine, Donald J., Heilveil, Andrew L., VanAken, Jerry R.
• Primary Examiner(s): Popek, Joseph A.
• Application Number:
  US07/520,986
• Time in Patent Office: 916 Days
• Field of Search: 365/189.02, 365/189.12, 365/219, 365/230.02, 365/230.09, 365/240, 340/798, 340/799, 340/800
• US Class Current: 365/219
• CPC Class Codes: G11C 7/1075 for multiport memories each having random access ports and serial ports, e.g. video RAM
• CPC Class Codes: H04N 5/907 using static stores, e.g. storage tubes or semiconductor memories H04N5/91 takes precedence

Abstract

In a video-type computer system and the like, an improved memory circuit is provided for adapting the system to CRT screens having different resolutions. The memory circuit includes a bit-mapped RAM unit or chip having sufficient cells to accommodate any CRT screen sought to be used, and also a serial shift register having taps at a plurality of different locations corresponding to different columns of cells in the RAM unit. When the RAM unit is in serial mode, a row of data is transferred into the serial shift register. Then the column address applied to the RAM unit is used to instruct and actuate a suitable decoder circuit to select the tap appropriate to unload the portion of the serial shift register containing the data bits of interest.

Claims

1. A storage device adapted for both random access and serial access modes of operation and responsive to a first signal, a second signal and a third signal, the storage device comprising:

a memory array having cells interconnected in rows and columns selectable in response to said first signal and said second signal,

register means having a plurality of bit positions selectively interconnectable with said columns of said memory array in response to said third signal and having a plurality of taps adjacent preselected bit locations therealong, and

tap selection means interconnected for selecting one of said taps in conjunction with said second signal.

2. The storage device described in claim 1, wherein said second signal that said tap selection means are responsive to includes an address signal and a selection signal.

3. The storage device described in claim 2, further including serial output means interconnectable with said selected tap.

4. The storage device described in claim 3, further comprising

row address means functionally interconnected with said rows of cells in said memory array and responsive to said first signal for addressing and selecting one of said rows of cells, and

column address means functionally interconnected with said columns of cells in said memory array and said tap selection means for addressing and selecting one of said columns of cells.

5. The storage device described in claim 4, wherein said first signal includes a row address signal and a row selection signal and said second signal includes a column address signal and a column selection signal.

6. The storage device described in claim 5, wherein said row address means are responsive to said row address signal and said row selection signal and said column address means and said tap selection means are responsive to said column address signal and said column selection signal.

7. The storage device described in claim 6, wherein said row address means are interconnected for addressing said rows of cells in said memory array in response to said row address signal and said column address means are interconnected for addressing said columns of cells in said memory array and said tap selection means in response to said column address signal.

8. The storage device described in claim 7, wherein said row address means are responsive to said row selection signal for selecting one of said rows of cells and said column address means are responsive to said column selection signal for selecting one of said columns of cells.

9. The storage device described in claim 8, wherein said tap selection means are responsive to said column selection signal for selecting one of said taps on said register means.

10. The storage device described in claim 9, wherein said column address means are responsive to said column address signal and said column selection signal when said memory array is in a random-access mode and said tap selection means are responsive to said column address signal and said column selection signal when said storage device is in a serial mode.

11. A dual port memory circuit having provision for both serial and random access, comprising

a memory component having a plurality of cells arranged in rows and columns interconnected by lines therein,

a serial register means having a plurality of bit positions each corresponding to and interconnectable with one of said column lines in said memory component,

a plurality of taps each interconnected with said register means at a different one of said bit positions thereon,

row address means interconnected with said memory component for selecting one of said row lines therein,

column address means interconnected with said memory component for selecting one of said column lines or one of said taps, and

output terminal means interconnected with said register means at a selected one of said taps in response to said column address means.

12. An improved video-type computer system, comprising

a data processing circuit for generating video data bits and a column address signal,

a memory circuit having a plurality of cells interconnected in rows and columns and responsive to said column address signal for receiving said video data bits,

a shift register having a plurality of bit positions for receiving stored video data bits from related columns of cells in said memory circuit,

a plurality of taps each interconnected with said shift register at preselected bit positions, and

selection means responsive to said column address signal for selecting one of said taps and unloading video data bits from a functionally related portion of said shift register.

13. The computer system described in claim 12, wherein said selection means selects said one tap and unloads the video data bits from said related portion of said shift register when said memory circuit is in serial mode.

14. The computer system described in claim 13, wherein said data processing circuit also generates a control signal for interconnecting said bit positions in said shift register to said related columns of cells in said memory circuit.

15. A memory device having both random access and serial access modes of operation, the memory device comprising;

a memory array including a plurality of storage cells arranged in addressable rows and columns for storing a bit of data in each storage cell,

a register having a plurality of storage positions for selectively connecting with the columns of storage cells of the memory array to transfer bits of data between the storage cells of the memory array and the storage positions of the register and having a plurality of taps, each tap being adjacent to a different one of the storage positions, and

a tap selector responsive to addresses for selectively coupling the plurality of taps with a terminal for transferring sequences of bits of data from the storage position adjacent the interconnected tap to the terminal.

16. A memory device, in accordance with claim 15, further comprising;

a row address circuit, responsive to addresses, for accessing one row of storage cells of the memory array at a time,

a column address circuit responsive to addresses, for accessing either one column of storage cells of the memory array or one tap adjacent a storage position of the register at a time.

17. A memory device, in accordance with claim 16, wherein

the one tap is selected for serial access of data from the register to the terminal in response to a column address signal and a column access strobe signal applied to the column address circuit.

18. A memory device, in accordance with claim 15, further comprising:

a transfer circuit interposed between the columns of storage cells and the register for selectively connecting the storage positions of the register with the columns of storage cells in response to a control signal.

19. A dual port memory circuit arranged for both serial access and random access, the memory circuit comprising:

a memory component having an array including a plurality of cells arranged in rows and columns,

a serial register having a plurality of storage elements, each corresponding to one of the columns of the array, the plurality of storage elements being selectively connectable to the columns of cells,

a plurality of taps, each interconnected with a different storage element of the serial register,

a row address circuit interconnected with the array for accessing a selected one of the rows of cells,

a terminal, and

a column address circuit interconnected with the memory component either for randomly accessing a selected one of the columns of cells or for selecting one of the taps for coupling a serial stream of data to the terminal.

20. A dual port memory circuit, in accordance with claim 19, further comprising:

a transfer circuit interposed between the columns of cells and the serial register for selectively connecting the storage elements of the serial register with the columns of cells in response to a control signal.

21. A dual port memory circuit, in accordance with claim 19, wherein

the one tap is selected in response to a column address signal and a column access strobe signal applied to the column address circuit.

22. A video display system comprising:

a data processor generating row addresses, column addresses, control signals and data bits representing an image,

a display device responsive to video signals for producing a visual image,

a dual port memory device arranged for both random and serial access for inputting data bits and outputting data bits, the memory device including

a plurality of cells arranged in rows and columns,

a serial register having a plurality of storage elements, each storage element corresponding to one of the columns of the memory components, and having a plurality of taps, each tap associated with a different one of the storage elements,

a row address circuit interconnected with the rows of cells for accessing a selected one of the rows of cells for writing or reading of data,

a column address circuit interconnected with the columns of cells for randomly accessing data stored in a selected column of cells and interconnected with the taps for serial access of the data stored in the serial register commencing at a selected storage element, and

a video signal shaping circuit, responsive to the serial data from the serial register, for producing the video signal and applying the video signal to the display device.

23. A video display system, in accordance with claim 22, further comprising:

a transfer circuit interposed between the columns of cells and the serial register for selectively connecting the storage elements of the serial register to the columns of cells in response to a control signal.

24. A video display system, in accordance with claim 22, wherein

the columns of cells are randomly accessed in response to a column address signal and a column access strobe signal applied to the column address circuit.

25. A video display system, in accordance with claim 22, wherein

a single tap is selected for serial access of data in response to a column address signal and a column access strobe signal applied to the column address circuit.

26. A storage device adapted for both random access and serial access modes of operation and responsive to a row address signal, a row access strobe signal, a column address signal, a column access strobe signal, and a transfer signal, the storage device comprising:

a memory array having cells arranged in addressable rows selectable in response to said row address signal, and said row access strobe signal and in addressable columns selectable in response to said column address signal and said column access strobe signal;

register means having a plurality of bit positions which are interconnectable with or disabled from connecting with said columns of said memory array in response to states of said transfer signal and having a plurality of taps adjacent preselected bit locations therealong; and

tap selection means interconnected with the register means for selecting one of said taps in conjunction with said column address signal and said column access strobe signal.

27. A storage device described in claim 26 further comprising

serial output means interconnectable with said selected tap.

28. A dual port memory circuit arranged for both serial access and random access, the memory circuit comprising:

a memory array having a plurality of cells arranged in addressable rows and columns;

a register having a plurality of storage elements, each storage element corresponding to one of the columns of the memory array, the plurality of storage elements being selectively connectable to the columns of cells;

a row address circuit interconnected with the memory array for randomly accessing a selected one of the rows of cells;

a column address circuit interconnected with the memory array for randomly accessing a selected one of the columns of cells;

a terminal interconnected with the register for writing a serial stream of data into the register;

the row address circuit accessing a first selected row of cells for storing the serial stream of data from the register; and

the row address circuit accessing a second selected row of cells for storing the same serial stream of data from the register without rewriting the serial stream of data into the register.

29. A memory circuit comprising:

a memory array having a plurality of cells arranged in addressable rows and columns;

a register having a plurality of storage elements, each storage element corresponding to one of the columns of the memory array, the plurality of storage elements being selectively connectable to the columns of cells;

a row address circuit interconnected with the memory array for randomly accessing a selected one of the rows of cells;

a column address circuit interconnected with the memory array for randomly accessing a selected one of the columns of cells;

the row address circuit accessing a first selected row of cells for transferring the selected row of data out of the cells into the register; and

the row address circuit accessing a second selected row of cells for transferring the data from the register into the second selected row of cells.

30. A video display system comprising:

a data processor generating row addresses, column addresses, control signals, and data bits representing an image;

a display device responsive to a serial sequence of data bits for producing a visual image;

a dual port memory device arranged for both random access for inputting data bits from the data processor and serial access for outputting data bits to the display device, the memory device including;

an array of storage cells positioned in addressable rows and columns;

a register including a plurality of storage elements and a plurality of taps;

a transfer circuit, responsive to a transfer signal, for enabling coupling between the storage elements and the storage cells;

row access circuitry, accessed contemporaneously with the transfer circuit, for transferring data bits from a row of storage cells to the storage elements;

tap access circuitry, responsive to a column address and a column address strobe, for selecting one of the taps for coupling the register to the display device; and

the register responsive to a clock signal for delivering a serial sequence of the data bits from the register by way of the selected tap to the display device for producing the visual image.

31. A memory arrangement comprising:

an array of storage cells positioned in addressable rows and columns;

a register including a plurality of storage elements and a plurality of taps;

a transfer circuit, responsive to a transfer signal, for enabling coupling between the storage elements and the storage cells;

row access circuitry accessed contemporaneously with the transfer circuit for transferring data from a row of storage cells to the storage elements;

tap access circuitry, responsive to a column address and a column address strobe, for selecting one of the taps for coupling the register to a serial data terminal; and

the register responsive to a clock signal for delivering a serial sequence of data by way of the selected tap to the serial data terminal.

32. A memory arrangement, in accordance with claim 31, further comprising:

column access circuitry, operating in concert with the row access circuitry and concurrently with the delivery of the serial sequence of data to the serial data terminal, for randomly accessing a selected one of the storage cells for a read or a write operation.