Method of making a vertical current flow field effect transistor
First Claim
1. A method for manufacturing a transistor comprising the steps of:
- providing a structure comprising a P-type first semiconductor region, a P-type second semiconductor region on said first region, said second region having a dopant concentration less than a dopant concentration of said first region, an N-type third semiconductor region formed on said second semiconductor region, and a P-type fourth semiconductor region formed on said third semiconductor region;
etching a trench through said fourth, third and second semiconductor regions;
forming an insulating layer in said trench, a portion of said insulating layer adjacent said first semiconductor region being thicker than a portion of said insulating layer adjacent said third semiconductor region; and
forming a gate in said trench.
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Accused Products
Abstract
A transistor constructed in accordance with our invention includes an N+ substrate, an N- region formed on the N+ substrate, a P- body region formed on the N- region, and an N+ source region formed on the P- body region. A vertical groove extends through the N+, P- and N- regions, and an insulating layer is formed on the groove walls. A polysilicon gate is formed inside the groove. Of importance, the portion of the insulating layer between the polysilicon and the N+ region and the insulating layer between the polysilicon and the N+ substrate is thicker than the portion of the insulating layer between the polysilicon gate and the P- body region. Because of the enhanced thickness of the portions of the insulating layer between the gate and N+ substrate, the transistor constructed in accordance with our invention is less susceptible to premature field induced breakdown.
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Citations
27 Claims
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1. A method for manufacturing a transistor comprising the steps of:
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providing a structure comprising a P-type first semiconductor region, a P-type second semiconductor region on said first region, said second region having a dopant concentration less than a dopant concentration of said first region, an N-type third semiconductor region formed on said second semiconductor region, and a P-type fourth semiconductor region formed on said third semiconductor region; etching a trench through said fourth, third and second semiconductor regions; forming an insulating layer in said trench, a portion of said insulating layer adjacent said first semiconductor region being thicker than a portion of said insulating layer adjacent said third semiconductor region; and forming a gate in said trench. - View Dependent Claims (2, 3, 4)
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5. A method for forming a transistor comprising the steps of:
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forming a structure comprising a first region of semiconductor material of a first dopant concentration and a first conductivity type, and a second region of semiconductor material of said first conductivity type and a second dopant concentration greater than said first dopant concentration formed on said first region; etching a plurality of grooves, said grooves extending through said second region and at least a portion of said first region; forming a plurality of insulating layers, each insulating layer within said plurality being formed in an associated one of said grooves, said insulating layers each having a first insulating region adjacent said first region having a first insulating region adjacent said first region of semiconductor material, said insulating layers each having a second insulating region adjacent said second region of semiconductor material, said second insulating region being thicker than said first insulating region; forming a gate structure within each of said grooves, said gate structure being insulated from said first and second regions by said insulating layers; and forming a plurality of semiconductor regions of a second conductivity type within said first region adjacent to said plurality of insulating layers for removing current carriers of said second conductivity type from said first region.
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6. A method for manufacturing a transistor comprising the steps of:
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providing a structure comprising a first semiconductor region of a first conductivity type, a second semiconductor region of said first conductivity type on said first region, said second region having a dopant concentration less than a dopant concentration of said first region, a third semiconductor region of a second conductivity type opposite said first conductivity type formed on said second semiconductor region, and a fourth semiconductor region of said first conductivity type formed on said third semiconductor region; etching a trench through said fourth, third and second semiconductor regions; forming an insulating layer in said trench, a portion of said insulating layer adjacent said first semiconductor region being thicker than a portion of said insulating layer adjacent said third semiconductor region; and forming a gate in said trench, wherein said insulating layer forming step comprises the steps of; masking sidewalls of said trench with a mask; forming an insulator on a surface of said trench below said mask; removing said mask from the sidewalls; and forming an insulator on a surface of said trench. - View Dependent Claims (7, 8, 9, 10)
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11. A method for manufacturing a transistor comprising the steps of:
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providing a structure comprising a first semiconductor region of a first conductivity type, a second semiconductor region of said first conductivity type on said first region, said second region having a dopant concentration less than a dopant concentration of said first region, a third semiconductor region of a second conductivity type opposite said first conductivity type formed on said second semiconductor region, and a fourth semiconductor region of said first conductivity type formed on said third semiconductor region; etching a trench through said fourth, third and second semiconductor regions; forming an insulating layer in said trench, a portion of said insulating layer adjacent said first semiconductor region being thicker than a portion of said insulating layer adjacent said third semiconductor region; and forming a gate in said trench, wherein said etching step comprises the steps of; etching said trench through said fourth region; and extending said trench at least through said third region; and wherein said process further comprises, between said step of etching through said fourth region and said extending step, the step of forming a first insulator on walls of said trench.
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12. A method of making a transistor comprising the steps of:
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providing a P-type first semiconductor region; providing a P-type second semiconductor region adjacent said first region, said second region having a dopant concentration less than a dopant concentration of said first region; providing an N-type third semiconductor region adjacent said second region; providing a P-type fourth semiconductor region adjacent said third region; etching a plurality of grooves through said fourth, third and second regions; forming an insulating layer in said grooves, a first portion of said insulating layer adjacent said first region being thicker than a second portion of said insulating layer adjacent said third region, said second portion being formed on sidewalls of said grooves; and forming a conductor in said grooves.
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13. A method for making a transistor comprising the steps of:
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providing a first semiconductor region of a first conductivity type; providing a second semiconductor region of said first conductivity type on said first region, said second region having a first portion having a dopant concentration less than a dopant concentration of said first region; forming a first groove in said second region; extending said first groove to at least said first region; forming a first insulator on a bottom of said first groove; forming a second insulator on the bottom and sidewalls of said first groove; and forming a first conductor in said groove, said method further comprising, between said groove forming and extending steps, the step of providing a third semiconductor region of a second conductivity type opposite said first conductivity type adjacent a bottom of said first groove and contained within said first portion. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. A method for making a transistor comprising the steps of:
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providing a first semiconductor region of a first conductivity type; providing a second semiconductor region of said first conductivity type on said first region, said second region having a first portion having a dopant concentration less than a dopant concentration of said first region; forming a first groove in said second region; extending said first groove to at least said first region; forming a first insulator on a bottom of said first groove; forming a second insulator on the bottom and sidewalls of said first groove; and forming a first conductor in said groove, wherein the step of forming the first insulator comprises the steps of; depositing a mask on a surface of said groove; etching said mask by a vertical etching process until at least a portion of said mask is removed from the bottom of said groove; and forming an insulator on the bottom of said groove.
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26. A method for making a transistor comprising the steps of:
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providing a first semiconductor region of a first conductivity type; providing a second semiconductor region of said first conductivity type on said first region, said second region having a first portion having a dopant concentration less than a dopant concentration of said first region; forming a first groove in said second region; extending said first groove to at least said first region; forming a first insulator on a bottom of said first groove; forming a second insulator on the bottom and sidewalls of said first groove; and forming a first conductor in said groove, said method further comprising, prior to said groove forming step, the steps of; forming a third insulator on said second region; and forming a mask on said third insulator; and wherein said method further comprises the steps of; forming a fourth insulator thicker than said third insulator over said conductor; forming an opening through said fourth insulator to said gate; removing said mask; etching said third and fourth insulators until said third insulator is removed; and forming a conductor in said opening and on said second region.
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27. A method for making a transistor comprising the steps of:
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providing a first semiconductor region of a first conductivity type; providing a second semiconductor region of said first conductivity type on said first region, said second region having a first portion having a dopant concentration less than a dopant concentration of said first region; forming a first groove in said second region; extending said first groove to at least said first region; forming a first insulator on a bottom of said first groove; forming a second insulator on the bottom and sidewalls of said first groove; and forming a first conductor in said groove, wherein said second region comprises a second portion having a dopant concentration higher than the dopant concentration of said first portion, and wherein said groove forming step comprises the steps of; forming a groove through said second portion; forming an insulator on walls of said groove through said second portion; and extending said groove.
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Specification