Method of making a vertical current flow field effect transistor

• US 5,164,325 A
• Filed: 10/08/1987
• Issued: 11/17/1992
• Est. Priority Date: 10/08/1987
• Status: Expired due to Fees

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Blanchard, Richard A., Cogan, Adrian I.
• Primary Examiner(s): Thomas, Tom
• Application Number:
  US07/107,725
• Time in Patent Office: 1,867 Days
• Field of Search: 437/38, 437/29, 437/40, 437/233, 437/235, 437/238, 437/228, 437/203, 437/979, 357/23.4, 156/643
• US Class Current: 438/270
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/739 controlled by field-effect, e.g. bipolar static induction transistors [BSIT] unijunction transistors H01L29/705
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7832 the structure comprising a MOS gate and at least one non-MOS gate, e.g. JFET or MESFET gate
• CPC Class Codes: Y10S 438/981 Utilizing varying dielectric thickness

Abstract

A transistor constructed in accordance with our invention includes an N+ substrate, an N- region formed on the N+ substrate, a P- body region formed on the N- region, and an N+ source region formed on the P- body region. A vertical groove extends through the N+, P- and N- regions, and an insulating layer is formed on the groove walls. A polysilicon gate is formed inside the groove. Of importance, the portion of the insulating layer between the polysilicon and the N+ region and the insulating layer between the polysilicon and the N+ substrate is thicker than the portion of the insulating layer between the polysilicon gate and the P- body region. Because of the enhanced thickness of the portions of the insulating layer between the gate and N+ substrate, the transistor constructed in accordance with our invention is less susceptible to premature field induced breakdown.

Claims

1. A method for manufacturing a transistor comprising the steps of:

providing a structure comprising a P-type first semiconductor region, a P-type second semiconductor region on said first region, said second region having a dopant concentration less than a dopant concentration of said first region, an N-type third semiconductor region formed on said second semiconductor region, and a P-type fourth semiconductor region formed on said third semiconductor region;

etching a trench through said fourth, third and second semiconductor regions;

forming an insulating layer in said trench, a portion of said insulating layer adjacent said first semiconductor region being thicker than a portion of said insulating layer adjacent said third semiconductor region; and

forming a gate in said trench.

2. The method of claim 1 wherein said step of etching a trench comprises the step of etching said trench through a portion of said first semiconductor region.

3. The method of claim 1, wherein a portion of said insulating layer adjacent said first and second regions is thicker than a portion of said insulating layer adjacent said third region.

4. The method of claim 1, wherein a portion of said insulating layer adjacent said fourth region is thicker than a portion of said insulating layer adjacent said third region.

5. A method for forming a transistor comprising the steps of:

forming a structure comprising a first region of semiconductor material of a first dopant concentration and a first conductivity type, and a second region of semiconductor material of said first conductivity type and a second dopant concentration greater than said first dopant concentration formed on said first region;

etching a plurality of grooves, said grooves extending through said second region and at least a portion of said first region;

forming a plurality of insulating layers, each insulating layer within said plurality being formed in an associated one of said grooves, said insulating layers each having a first insulating region adjacent said first region having a first insulating region adjacent said first region of semiconductor material, said insulating layers each having a second insulating region adjacent said second region of semiconductor material, said second insulating region being thicker than said first insulating region;

forming a gate structure within each of said grooves, said gate structure being insulated from said first and second regions by said insulating layers; and

forming a plurality of semiconductor regions of a second conductivity type within said first region adjacent to said plurality of insulating layers for removing current carriers of said second conductivity type from said first region.

6. A method for manufacturing a transistor comprising the steps of:

providing a structure comprising a first semiconductor region of a first conductivity type, a second semiconductor region of said first conductivity type on said first region, said second region having a dopant concentration less than a dopant concentration of said first region, a third semiconductor region of a second conductivity type opposite said first conductivity type formed on said second semiconductor region, and a fourth semiconductor region of said first conductivity type formed on said third semiconductor region;

etching a trench through said fourth, third and second semiconductor regions;

forming an insulating layer in said trench, a portion of said insulating layer adjacent said first semiconductor region being thicker than a portion of said insulating layer adjacent said third semiconductor region; and

forming a gate in said trench,

wherein said insulating layer forming step comprises the steps of;

masking sidewalls of said trench with a mask;

forming an insulator on a surface of said trench below said mask;

removing said mask from the sidewalls; and

forming an insulator on a surface of said trench.

7. The method of claim 6 wherein said step of forming an insulator on a surface of said trench below said mask comprises the step of thermally growing SiO₂.

8. The method of claim 6, wherein said masking step comprises:

depositing said mask on said structure and a surface of said trench, and

etching said mask by a vertical etching process until at least a portion of said mask is removed from a bottom of said trench.

9. The method of claim 8, wherein said first, second and third regions contain silicon;

wherein said depositing step comprises depositing Si₃ N₄ by chemical vapor deposition; and

wherein each said insulator forming step comprises a step of growing SiO₂.

10. The method of claim 6, further comprising, after said masking step, the step of extending said trench into said first region.

11. A method for manufacturing a transistor comprising the steps of:

providing a structure comprising a first semiconductor region of a first conductivity type, a second semiconductor region of said first conductivity type on said first region, said second region having a dopant concentration less than a dopant concentration of said first region, a third semiconductor region of a second conductivity type opposite said first conductivity type formed on said second semiconductor region, and a fourth semiconductor region of said first conductivity type formed on said third semiconductor region;

etching a trench through said fourth, third and second semiconductor regions;

forming an insulating layer in said trench, a portion of said insulating layer adjacent said first semiconductor region being thicker than a portion of said insulating layer adjacent said third semiconductor region; and

forming a gate in said trench,

wherein said etching step comprises the steps of;

etching said trench through said fourth region; and

extending said trench at least through said third region; and

wherein said process further comprises, between said step of etching through said fourth region and said extending step, the step of forming a first insulator on walls of said trench.

12. A method of making a transistor comprising the steps of:

providing a P-type first semiconductor region;

providing a P-type second semiconductor region adjacent said first region, said second region having a dopant concentration less than a dopant concentration of said first region;

providing an N-type third semiconductor region adjacent said second region;

providing a P-type fourth semiconductor region adjacent said third region;

etching a plurality of grooves through said fourth, third and second regions;

forming an insulating layer in said grooves, a first portion of said insulating layer adjacent said first region being thicker than a second portion of said insulating layer adjacent said third region, said second portion being formed on sidewalls of said grooves; and

forming a conductor in said grooves.

13. A method for making a transistor comprising the steps of:

providing a first semiconductor region of a first conductivity type;

providing a second semiconductor region of said first conductivity type on said first region, said second region having a first portion having a dopant concentration less than a dopant concentration of said first region;

forming a first groove in said second region;

extending said first groove to at least said first region;

forming a first insulator on a bottom of said first groove;

forming a second insulator on the bottom and sidewalls of said first groove; and

forming a first conductor in said groove,

said method further comprising, between said groove forming and extending steps, the step of providing a third semiconductor region of a second conductivity type opposite said first conductivity type adjacent a bottom of said first groove and contained within said first portion.

14. The method of claim 13, further comprising, between said groove forming step and said step of providing said third region, the step of forming an insulator on walls of said groove.

15. The method of claim 13, wherein said step of providing said third region comprises the step of introducing a dopant of said second conductivity type into a portion of said second region at the bottom of said groove.

16. The method of claim 13, further comprising the steps of:

forming a second groove in said second region;

providing a fourth semiconductor region of said second conductivity type adjacent a bottom of said second groove and contiguous with said third region;

forming a third insulator on a surface of said second groove;

forming a second conductor in said second groove;

forming a third groove through said second conductor and through said third insulator to said fourth region; and

forming a third conductor in said third groove.

17. The method of claim 16, wherein said third groove is substantially V-shaped.

18. The method of claim 16, wherein said second groove is contiguous with said first groove.

19. The method of claim 16, further comprising the steps of:

prior to said steps of forming said first and second grooves, forming a fourth insulator on said second region;

prior to said step of forming said third groove;

forming a fifth insulator on said first and second conductors, a portion of said fifth insulator over said first conductor being thicker than said first insulator;

forming a sixth insulator on a bottom of said third groove; and

etching said fourth, fifth and sixth insulators until said fourth and sixth insulators are removed;

and wherein said step of forming said third conductor comprises the step of forming a conductor on said second region.

20. The method of claim 13, further comprising the step of providing a fourth semiconductor region of said first conductivity type between said third region and said first groove, a dopant concentration of said fourth region being higher than a dopant concentration of said first portion of said second

21. The method of claim 20, further comprising the step of providing an electrical contact between said fourth region and said first conductor,

wherein said conductor is a semiconductor region of said first conductivity type.

22. The method of claim 13, further comprising the steps of:

forming a second groove in said second region;

providing a fourth semiconductor region of said second conductivity type adjacent a bottom of said second groove and contiguous with said third region;

providing a fifth semiconductor region of said first conductivity type between said third region and said first groove, a dopant concentration of said fifth region being higher than a dopant concentration of said first portion of said second region;

providing a sixth semiconductor region of said first conductivity type between said fourth region and said second groove, a dopant concentration of said sixth region being higher than a dopant concentration of said first portion, said sixth region being contiguous with said fifth region;

forming a third insulator on walls of said second groove; and

forming a second conductor in said second groove in electrical contact with said sixth region, said second conductor being a semiconductor region of said first conductivity type.

23. The method of claim 22, wherein said second groove is contiguous with said first groove, and

wherein said second conductor is contiguous with said first conductor.

24. The method of claim 22, wherein said step of forming said first insulator comprises the steps of:

depositing a mask on a surface of said first and second grooves;

removing said mask off the bottom of said first groove; and

forming an insulator on the bottom of said first groove.

25. A method for making a transistor comprising the steps of:

providing a first semiconductor region of a first conductivity type;

providing a second semiconductor region of said first conductivity type on said first region, said second region having a first portion having a dopant concentration less than a dopant concentration of said first region;

forming a first groove in said second region;

extending said first groove to at least said first region;

forming a first insulator on a bottom of said first groove;

forming a second insulator on the bottom and sidewalls of said first groove; and

forming a first conductor in said groove,

wherein the step of forming the first insulator comprises the steps of;

depositing a mask on a surface of said groove;

etching said mask by a vertical etching process until at least a portion of said mask is removed from the bottom of said groove; and

forming an insulator on the bottom of said groove.

26. A method for making a transistor comprising the steps of:

providing a first semiconductor region of a first conductivity type;

providing a second semiconductor region of said first conductivity type on said first region, said second region having a first portion having a dopant concentration less than a dopant concentration of said first region;

forming a first groove in said second region;

extending said first groove to at least said first region;

forming a first insulator on a bottom of said first groove;

forming a second insulator on the bottom and sidewalls of said first groove; and

forming a first conductor in said groove, said method further comprising, prior to said groove forming step, the steps of;

forming a third insulator on said second region; and

forming a mask on said third insulator;

and wherein said method further comprises the steps of;

forming a fourth insulator thicker than said third insulator over said conductor;

forming an opening through said fourth insulator to said gate;

removing said mask;

etching said third and fourth insulators until said third insulator is removed; and

forming a conductor in said opening and on said second region.

27. A method for making a transistor comprising the steps of:

providing a first semiconductor region of a first conductivity type;

providing a second semiconductor region of said first conductivity type on said first region, said second region having a first portion having a dopant concentration less than a dopant concentration of said first region;

forming a first groove in said second region;

extending said first groove to at least said first region;

forming a first insulator on a bottom of said first groove;

forming a second insulator on the bottom and sidewalls of said first groove; and

forming a first conductor in said groove,

wherein said second region comprises a second portion having a dopant concentration higher than the dopant concentration of said first portion, and

wherein said groove forming step comprises the steps of;

forming a groove through said second portion;

forming an insulator on walls of said groove through said second portion; and

extending said groove.