Computer aided design system capable of placing functional blocks with a circuit constraint satisfied

• US 5,164,907 A
• Filed: 02/14/1990
• Issued: 11/17/1992
• Est. Priority Date: 02/15/1989
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Yabe, Shoji
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): Cosimano, Edward R.
• Application Number:
  US07/479,679
• Time in Patent Office: 1,007 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491
• US Class Current: 716/112
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

A system and method for logic circuit design in which functional blocks are placed on a substantially plane area in compliance with logic connection information under a circuit constraint. Critical nets are first extracted from logic connection information and then, critical blocks connected to the critical nets are extracted from the logic connection information. The critical blocks are initially placed on the substantially plane area to provide an initial critical block placement result. The initial critical block placement result is iteratively improved until the circuit constraint is satisfied.

Claims

1. A method of designing by computer a logic circuit comprising a plurality of functional blocks connected through path nets to place said functional blocks, including critical blocks, on a substantially plane area in response to logic connection information and under a circuit constraint, said logic connection information indicating connection between said functional blocks, said method comprising the steps of:

extracting critical nets comprising predetermined parts of said path nets from said logic connection information, by critical net extracting means;

extracting critical blocks connected to said critical nets from said logic connection information, by critical block extracting means;

initially placing said critical blocks on said substantially plane area to provide an initial critical block placement result, by critical block placing means;

checking whether or not said initial critical block placement result satisfies said circuit constraint, by checking means; and

iteratively improving said initial critical block placement result until said circuit constraint is satisfied, by critical block placement improving means, if said initial critical block placement result does not satisfy said circuit constraint.

2. A method as claimed in claim 1 in which said functional blocks include normal blocks, said method further comprising the steps of:

initially placing normal blocks identical with said functional blocks except for said critical blocks on said substantially plane area to provide an initial normal block placement result, by normal block placing means, and

improving said initial normal block placement result, by normal block placement improving means, if said initial normal block placement result does not satisfy said circuit constraint.

3. A computer aided design system for designing a logic circuit comprising a plurality of functional blocks connected through path nets to one another to place said functional blocks on a substantially plane area in response to logic connection information and under a circuit constraint, said logic connection information indicating connections between said functional blocks, said system comprising:

logic connection information memorizing means for memorizing said logic connection information as stored logic connection information;

critical net extracting means connected to said logic connection information memorizing means for extracting, as critical nets, predetermined parts of said path nets from said stored logic connection information to produce critical net information indicative of said critical nets;

critical net memorizing means connected to said critical net extracting means for memorizing said critical net information as stored critical net information;

critical block extracting means connected to said logic connection information memorizing means and to said critical net memorizing means for extracting critical blocks connected to said critical nets from said stored logic connection information in accordance with said stored critical net information to produce critical block information indicative of said critical blocks;

critical block initial placing means connected to said critical block extracting means and to said critical net memorizing means for carrying out initial placement of said critical blocks on said substantially plane area in accordance with said stored critical net information to produce initial critical block placement result information indicative of an initial critical block placement result;

critical block placement result memorizing means connected to said critical block initial placing means for memorizing, as stored critical block placement result information, one of said initial critical block placement result information and improved critical block placement result information;

circuit constraint memorizing means for memorizing circuit constraint information indicative of said circuit constraint as stored circuit constraint information;

critical block placement result checking means connected to said critical block placement result memorizing means and to said circuit constraint memorizing means for using said stored circuit constraint information in checking whether or not said stored critical block placement result information satisfies said circuit constraint, said critical block placement result checking means producing improvement indication information when said stored critical block placement result information does not satisfy said circuit constraint;

interative critical block placement improving means connected to said critical block placement result checking means and to said critical block placement result memorizing means for interatively improving said stored critical block placement result information in response to said improvement indication information to produce one of said improved critical block placement result information that indicates an improved critical block placement result; and

supplying means connected to said iterative critical block placement improving means and to said critical block placement result memorizing means for supplying said critical block placement result memorizing means with said one of said improved critical block placement result information.

4. A computer aided design system as claimed in claim 3, wherein said critical block placement result checking means produces circuit constraint satisfaction information when said stored critical block placement result information satisfies said circuit constraint, and said system further comprising:

normal block initial placing means connected to said critical block placement result checking means and to said logic connection information memorizing means for carrying out initial placement of normal blocks identical with said functional blocks except for said critical blocks on said substantially plane area to provide initial normal block placement result information indicative of an initial normal block placement result; and

normal block placement improving means connected to said normal block initial placing means for improving said initial normal block placement result information unitl normal block placement result information satisfies said circuit constraint.

5. A method designing by computer a logic circuit comprising a plurality of functional blocks connected through path nets to place said functional blocks on a substantially plane area in response to logic connection information and under a circuit constraint, said logic connection information indicating connections between said functional blocks, said method comprising the steps of:

extracting critical nets comprising predetermined parts of said path nets from said logic connection information, by critical net extracting means;

extracting critical blocks connected to said critical nets from said logic connection information, by critical block extracting means;

placing said critical blocks on said substantially plane area to provide a critical block placement result, by critical block placing means;

checking whether or not said critical block placement result satisfies said circuit constraint, by checking means; and

iteratively improving said critical block placement result until said circuit constraint is satisfied, by improving means, if said checking step indicates said critical block placement result does not satisfy said circuit constraint.

6. A method as claimed in claim 5, said method further comprising the steps of:

placing normal blocks identical with said functional blocks except for said critical blocks on said substantially plane area to provide a normal block placement result, by normal block placing means; and

improving said normal block placement result, by normal block placement improving means, until said normal block placement result satisfies said circuit constraint.