Information processing system

• US 5,165,010 A
• Filed: 01/04/1990
• Issued: 11/17/1992
• Est. Priority Date: 01/06/1989
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Hirai, Yuzo, Doi, Toshio, Yamada, Minoru, Yagyu, Masayoshi, Masuda, Noboru, Ishibashi, Kenichi, Asai, Mitsuo, Masaki, Akira, Hayashi, Takehisa, Yasunaga, Moritoshi
• Primary Examiner(s): MacDonald, Allen R.
• Application Number:
  US07/461,080
• Time in Patent Office: 1,048 Days
• Field of Search: 364/513, 364/807, 364/200, 364/900, 340/172.5, 395/24, 395/27
• US Class Current: 706/42
• CPC Class Codes: G06N 3/04 Architecture, e.g. interconnection topology
• CPC Class Codes: G06N 3/063 using electronic means

Abstract

An information processing system includes a plurality of functional blocks (neurons) and a data bus for transmitting in common the outputs of the individual functional blocks (neurons). Data transaction among the functional blocks (neurons) is performed through the data bus on the time-division basis. For preventing the outputs from conflicting or competition, addresses are assigned to the individual blocks (neurons), respectively, so that only the functional blocks (neuron) having the own address designated by the address signal supplied through an address bus outputs data signal onto the data bus, while the other functional blocks (neurons) receive the information on the data bus as the signal originating in the functional block whose address is designated at that time point. The addresses are sequentially changed. During a round of the address signals, data are transmitted from given functional blocks (neurons) to other given functional blocks (neurons).

Claims

1. An information processing system, comprising:

a plurality of neurons each having a memory for storing a weight value which is related to the other neurons;

means for generating an address signal for specifying sequentially one by one said plurality of neurons;

an address bus, connected to said means for generating and each neuron, for transmitting said address signal; and

a data bus, connected to each neuron, for transmitting an output signal value from each neuron to the other neurons;

wherein each neuron determines its output signal value in accordance with a total sum of products of its associated weight value and the output signal values of the other neurons, and one of said neurons which is specified by said address signal sends out an output signal value to said data bus.

2. An information processing system according to claim 1, wherein when said generating means generates a predetermined address signal which specifies none of said neurons, means for moving said system to various states moves said system to a predetermined state.

3. An information processing system according to claim 2, wherein each neuron includes means for temporarily storing the output signal value of said each neuron.

4. An information processing system according to claim 1, wherein said plurality of neurons are each identified as belonging to a plurality of groups, and wherein said address bus and said data bus are constituted, respectively, by first buses each connecting neurons within each of said groups and second buses for connecting said first buses.

5. An information processing system according to claim 4, wherein each of said second buses is wired by using a conductor having a greater bit width than that for each of said first buses.

6. An information processing system according to claim 4, further including a clock bus for supplying a clock signal to each of said neurons, wherein transmission between each of said first buses and each of said second buses is synchronized to occur when said clock signal is in a predetermined state.

7. An information processing system according to claim 1, wherein some of said neurons reside on a semiconductor wafer.

8. An information processing system according to claim 1, wherein each neuron includes address translation means for performing a predetermined translation for an address signal being input to said each neuron for thereby outputting onto said address bus an address signal differing from said inputted address signal.

9. An information processing system according to claim 8, wherein said address translation means is constituted by means for adding or deleting at least one bit to or from said inputted address signal.

10. An information processing system according to claim 8, wherein each of said neurons includes an address decoder for decoding said address signal when said address signal corresponds to a predetermined address signal.

11. An information processing system according to claim 1, wherein said memory stores a predetermined number of weight values in an order starting from a maximum absolute value of said weight values.

12. An information processing system, comprising:

a plurality of neurons each having a memory for storing a weight value which is related to the other neurons;

means for generating an address signal for specifying sequentially one by one said plurality of neurons;

an address bus, connected to said means for generating and each neuron, for transmitting said address signal; and

a data bus, connected to each neuron, for transmitting an output signal value from each neuron to at least one of the other neurons;

wherein each neuron determines its output signal value in accordance with a total sum of products of its associated weight value and the output signal values of the other neurons, and one of said neurons which is specified by said address signal sends out an output signal value to said data bus.

13. An information processing method in an information processing system including a plurality of neurons each having a memory, said neurons being connected to each other by a data bus and an address bus, said method comprising the steps of:

storing a weight value in each memory related to the other neurons;

generating an address signal for specifying sequentially one by one some of said plurality of neurons;

transmitting on said address bus said address signal; and

transmitting one said data bus an output signal value from each neuron to at least one of the other neurons;

wherein each neuron determines its output signal value in accordance with a total sum of products of its associated weight value and the output signal values of the other neurons, and one of said neurons which is specified by said address signal sends out an output signal value to said data bus.

14. An information processing system including a plurality of neurons each having a memory, said system comprising:

means for generating an address signal for specifying sequentially one by one said plurality of neurons;

an address bus, connected to said means for generating and each neuron, for transmitting said address signal; and

a data bus, connected to each neuron, for transmitting an output signal value from each neuron to the other neurons;

wherein each memory has prestored therein a weight value which is related to the other neurons; and

wherein each neuron determines its output signal value in accordance with a total sum of products of its associated weight value and the output signal values of the other neurons, and one of said neurons which is specified by said address signal sends out an output signal value to said data bus.

15. An information processing method in an information processing system including a plurality of neurons each having a memory, said neurons being connected to each other by a data bus and an address bus, said method comprising the steps of:

storing in each memory a weight value related to the other neurons;

generating an address signal for specifying sequentially one by one some of said plurality of neurons;

transmitting on said address bus said address signal; and

transmitting one said data bus an output signal value from each neuron to at least one of the other neurons;

wherein each neuron determines its output signal value in accordance with a total sum of products of its associated weight value and the output signal values of the other neurons, and one of said neurons which is specified by said address signal sends out an output signal value to said data bus.

16. An information processing method according to claim 15, wherein when said generating step generates a predetermined address signal which does not specify any of said neurons said method further comprises the steps of:

transmitting on said address bus said predetermined address signal; and

moving said information processing system to a predetermined state.

17. An information processing method according to claim 16, further comprising the step of:

temporarily storing in each neuron the output signal value from said each neuron corresponding to said transmitted predetermined address signal.

18. An information processing method according to claim 15, further comprising the step of:

storing in each neuron a predetermined number of weight values in an order starting from a maximum absolute value of said weight values.