Parallel processing system with processor array and network communications system for transmitting messages of variable length

• US 5,165,023 A
• Filed: 12/17/1986
• Issued: 11/17/1992
• Est. Priority Date: 12/17/1986
• Status: Expired due to Fees

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Gifford, David K.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): KULIK, PAUL V
• Application Number:
  US06/943,375
• Time in Patent Office: 2,162 Days
• Field of Search: 340/825.03, 340/826, 340/827, 340/825.52, 340/825.53, 364/200 MS File, 364/900 MS File, 370/54, 370/60
• US Class Current: 710/317
• CPC Class Codes: G06F 15/17368 non hierarchical topologies

Abstract

A highly-parallel processing system in which a number of processing elements are interconnected by a network, and are also connected to a system bus and are controlled by a central processing unit. Each processing element includes a memory, and all of the memories in the processing elements form at least part of the memory available to the CPU. The processing elements normally execute programs in MIMD mode, and the CPU or another unit can interrupt them to execute a SIMD instruction. The network allows for transmission of variable length messages and also for combining messages when received at a common processing element.

Claims

1. A parallel processing array including a plurality of processing elements and an interconnection network for transferring messages among the processing elements, each processing element including network interface means and means for generating a message in the form of one or more blocks, said message including a destination address field, said network interface means including:

A. a plurality of receive circuit means each connected to receive message blocks from a transmit circuit means of a connected processing element;

B. a plurality of transmit circuit means each connected to transmit message blocks to a receive circuit means of a connected processing element;

C. transfer means for coupling the message blocks from any one of said receive circuit means to any one of said transmit circuit means in response to the contents of a destination address field, comprising;

i. switch means for controllably coupling the message blocks received in any one of said receive circuit means to any one of said transmit circuit means,

ii. routing circuit control means connected to said switch means and to each of said receive circuit means, including means for (a) storing a correspondence between a destination address and one of said transmit circuit means, (b) reading the destination address field from a message, (c) identifying, in response to the destination address field of said message, a corresponding one of said transmit circuit means, and then enabling said switch means to couple all blocks of said message thereafter received by any of said receive circuit means to said corresponding one of said transmit circuit means, and (d) when the last block of said message is received by one of said receive circuit means, disabling said switch means after said last block is coupled to said corresponding one of said transmit circuit means.

2. An array as defined in claim 1 wherein

each said processing element further includes processor means which generates and receives messages,

each associated network interface means further includes outbound circuit means for receiving messages from said processor means and inbound circuit means for transmitting messages to said processor means, and

said switch means further includes means for coupling a message from said outbound circuit means to any one of said transmit circuit means and from any one of said receive circuit means to said inbound circuit means under direction of said routing circuit control means.

3. An array as defined in claim 2 wherein

each message further includes a combine field indicating whether said message should be combined with another message,

each said network interface means further includes combine determination means for notifying said routing circuit control means that the destination address field and combine fields of two messages have a common value, and

said routing circuit control means controls said switch means in response to notification from said combine determination means.

4. An array as defined in claim 3 wherein

said routing circuit control means directs said switch means to couple the messages to said inbound circuit means in response to notification from said combine determination means.

5. An array as defined in claim 2 wherein

said message blocks include start blocks, middle blocks, and end blocks, each block having a type field to identify the type of block and a data field, the start blocks further including said destination address field, and

said routing circuit control means includes:

message reading means for iteratively reading the message blocks contained in each of said receive circuit means and for obtaining the contents of the type and destination address fields contained therein;

routing memory means connected to said message reading means, said routing memory means storing said correspondence and identifying one of said transmit circuit means in response to a destination address received from said message reading means; and

switch control means connected to said routing memory means, said switch control means controlling said switch means in response to the identification of one of said transmit circuit means by said routing memory means.

6. An array as defined in claim 5 wherein said routing memory means includes a plurality of identification circuits, each including:

key storage means for storing a match criterion,

transmit circuit identification storage means for storing an identification of one of said transmit circuit means;

enabling means connected to said key storage means, said message reading means, and said switch control means for enabling said transmit circuit identification storage means to send said stored identification to said switch control means if the destination address received from said message reading means corresponds to said match criterion.

7. An array as defined in claim 6 wherein each enabling means has a predetermined priority relative to the enabling means of other identification circuits, each enabling means including

a comparison means connected to the key storage means and the message reading means of said enabling means, said comparison means generating a match signal if the destination address received from said message reading means corresponds to the match criterion stored in said key storage means;

a priority means connected to said comparison means, the comparison means of other identification circuits, and said transmit circuit identification storage means, said priority means enabling said transmit circuit identification storage means to send said stored identification if said match signal is being generated and the comparison means of other enabling means which have a higher priority are not generating a match signal.

8. An array as defined in claim 7 wherein said routing memory means includes a common priority bus, and the priority means of each said identification circuit includes

priority level storage means for storing a priority level value;

match signal driver means connected to the comparison means and priority level storage means of said priority means, and said priority bus, for driving the priority level stored in said priority level storage means onto said priority bus if said comparison means is generating a match signal; and

priority comparison means connected to said priority level storage means and said priority bus for enabling the transmit circuit identification storage means of said identification circuit to send said stored identification if the priority level value stored by said priority level storage means corresponds to the signals on the priority bus.

9. An array as defined in claim 8 wherein

all of the key storage means, priority level means, and transmit circuit storage identification means of each processing element are connected to the processor means of said processing element, and

said processor means includes means for enabling match criteria, priority level values, and identifications of transmit circuit means, to be respectively transferred into said key storage means, priority level storage means, and transmit circuit storage identification means.

10. An array as defined in claim 6 wherein

said key storage means includes means for storing a first match criterion relating to a receive circuit means and means for storing a second match criterion relating to a destination address, and

said enabling means receives from said message reading means both the contents of the destination address field and the identification of the receive circuit means storing the destination address field and relates them to said first and second match criteria respectively to determine whether the match criteria are satisfied.

11. An array as defined in claim 1 wherein the switch means of each said processing element includes

a transfer bus, and

transfer gate means connected to each receive circuit means of said processing element and said bus, said transfer gate means iteratively gating the message from one of said receive circuit means onto said bus and enabling the message on said bus to be received by a selected one of said transmit circuit means.

12. A parallel processing array including a plurality of processing elements and an interconnection network for transferring messages among the processing elements, each processing element including network interface means and means for generating messages, each message comprising a sequence of message signals, including a destination address field, which are transmitted in serial form, said network interface means including:

A. a plurality of receive circuit means each connected to another processing element via a receive line, each including;

i. receive shift register means for sequentially receiving and storing serial message signals during a message transfer interval,

ii. error checking means connected to said receive shift register means for generating a receive acknowledgement signal in response to the correct receipt of said message,

iii. acknowledgement signal receiving means for receiving, during an acknowledgement signal transfer interval, an acknowledgement signal from the error checking means of the connected processing element,

iv. receiver coupling means connected to said receive shift register means, said acknowledgement signal receiving means and said receive line for selectively coupling signals from said receive line to said receive shift register means during said message transfer interval and to said acknowledgement signal receiving means during said acknowledgement signal transfer interval, and

v. receive message storage means connected to said error checking means and said receive shift register means for retrieving a message stored in said receive shift register means in response to a determination by said error checking means that said message was correctly received;

B. a plurality of transmit circuit means each connected to another processing element via a transmit line, each including;

i. transmit message storage means for storing a message,

ii. transmit shift register means connected to said transmit message storage means for retrieving a message from said transmit message storage means and sequentially transmitting serial message signals during said message transfer interval,

iii. transmitter coupling means connected to said transmit shift register means, said error checking means, and said transmit line for selectively coupling signals onto said transmit line from said transmit shift register means during said message transfer interval and to said error checking means during said acknowledgement signal transfer interval;

C. transfer means for coupling the message signals of each received message from any one of said receive message storage means to any one of said transmit message storage means in response to the contents of a destination address field comprising;

i. switch means for controllably coupling the message signals received in any one of said receive message storage means to any one of said transmit storage means,

ii. routing circuit control means connected to said switch means, each of said receive circuit means, and to each of said receiver and transmitter coupling means, said routing circuit control means including means for (a) storing a correspondence between a destination address and one of said transmit circuit means, (b) reading the destination address field from a message, (c) identifying, in response to the destination address field of said message, a corresponding one of said transmit circuit means, and then enabling said switch means to couple all message signals of said message to said corresponding transmit circuit means, and (d) establishing said message transfer interval and said acknowledgment signal transfer interval by enabling said receiver and transmitter coupling means to respectively couple to said acknowledgement signal receiving means and said error checking means, and then to said receive and transmit shift register means.

13. A processing element for use in a parallel processing array including a plurality of processing elements and an interconnection network for transferring messages among the processing elements, said processing element including network interface means and means for generating a message in the form of one or more blocks, said message including a destination address field, said network interface means including:

A. a plurality of receive circuit means each connected to receive message blocks from a transmit circuit means of a connected processing element;

B. a plurality of transmit circuit means each connected to transmit message blocks to a receive circuit means of a connected processing element;

C. transfer means for coupling the message blocks from any one of said receive circuit means to any one of said transmit circuit means in response to the contents of a destination address field, comprising;

i. switch means for controllably coupling the message blocks received in any one of said receive circuit means to any one of said transmit circuit means,

ii. routing circuit control means connected to said switch means and to each of said receive circuit means, including means for (a) storing a correspondence between a destination address and one of said transmit circuit means, (b) reading the destination address field from a message, (c) identifying, in response to the destination address field of said message, a corresponding one of said transmit circuit means, and then enabling said switch means to couple all blocks of said message thereafter received by any of said receive circuit means to said corresponding one of said transmit circuit means, and (d) when the last block of said message is received by one of said receive circuit means, disabling said switch means after said last block is coupled to said corresponding one of said transmit circuit means.

14. A processing element as defined in claim 13 wherein

said processing element further includes processor means which generates and receives messages,

said network interface means further includes outbound circuit means for receiving messages from said processor means and inbound circuit means for transmitting messages to said processor means, and

said switch means further includes means for coupling a message from said outbound circuit means to any one of said transmit circuit means and from any one of said receive circuit means to said inbound circuit means under direction of said routing circuit control means.

15. A processing element as defined in claim 14 wherein

each message further includes a combine field indicating whether said message should be combined with another message,

said network interface means further includes combine determination means for notifying said routing circuit control means that the destination address field and combine fields of two messages have a common value, and

said routing circuit control means controls said switch means in response to notification from said combine determination means.

16. A processing element as defined in claim 15 wherein

said routing circuit control means directs said switch means to couple the messages to said inbound circuit means in response to notification from said combine determination means.

17. A processing element as defined in claim 14 wherein

said message blocks include start blocks, middle blocks, and end blocks, each block having a type field to identify the type of block and a data field, the start blocks further including said destination address field, and

said routing circuit control means includes:

message reading means for iteratively reading the message blocks contained in each of said receive circuit means and for obtaining the contents of the type and destination address fields contained therein;

routing memory means connected to said message reading means, said routing memory means storing said correspondence and identifying one of said transmit circuit means in response to a destination address received from said message reading means; and

switch control means connected to said routing memory means, said switch control means controlling said switch means in response to the identification of one of said transmit circuit means by said routing memory means.

18. A processing element as defined in claim 17 wherein said routing memory means includes a plurality of identification circuits, each including:

key storage means for storing a match criterion,

transmit circuit identification storage means for storing an identification of one of said transmit circuit means;

enabling means connected to said key storage means, said message reading means, and said switch control means for enabling said transmit circuit identification storage means to send said stored identification to said switch control means if the destination address received from said message reading means corresponds to said match criterion.

19. A processing element as defined in claim 18 wherein each enabling means has a predetermined priority relative to the enabling means of other identification circuits, each enabling means including

a comparison means connected to the key storage means and the message reading means of said enabling means, said comparison means generating a match signal if the destination address received from said message reading means corresponds to the match criterion stored in said key storage means;

a priority means connected to said comparison means, the comparison means of other identification circuits, and said transmit circuit identification storage means, said priority means enabling said transmit circuit identification storage means to send said stored identification if said match signal is being generated and the comparison means of other enabling means which have a higher priority are not generating a match signal.

20. A processing element as defined in claim 19 wherein said routing memory means includes a common priority bus, and the priority means of each said identification circuit includes

priority level storage means for storing a priority level value;

match signal driver means connected to the comparison means and priority level storage means of said priority means, and said priority bus, for driving the priority level stored in said priority level storage means onto said priority bus if said comparison means is generating a match signal; and

priority comparison means connected to said priority level storage means and said priority bus for enabling the transmit circuit identification storage means of said identification circuit to send said stored identification if the priority level value stored by said priority level storage means corresponds to the signals on the priority bus.

21. A processing element as defined in claim 20 wherein

all of the key storage means, priority level means, and transmit circuit storage identification means of said processing element are connected to the processor means, and

said processor means includes means for enabling match criteria, priority level values, and identifications of transmit circuit means, to be respectively transferred into said key storage means, priority level storage means, and transmit circuit storage identification means.

22. A processing element as defined in claim 18 wherein

said key storage means includes means for storing a first match criterion relating to a receive circuit means and means for storing a second match criterion relating to a destination address, and

said enabling means receives from said message reading means both the contents of the destination address field and the identification of the receive circuit means storing the destination address field and relates them to said first and second match criteria respectively to determine whether the match criteria are satisfied.

23. A processing element as defined in claim 13 wherein said switch means includes

a transfer bus, and

transfer gate means connected to each of said receive circuit means and said bus, said transfer gate means iteratively gating the message from one of said receive circuit means onto said bus and enabling the message on said bus to be received by a selected one of said transmit circuit means.

24. A processing element for use in a parallel processing array including a plurality of processing elements and an interconnection network for transferring messages among the processing elements, said processing element including network interface means and means for generating messages, each message comprising a sequence of message signals, including a destination address field, which are transmitted in serial form, said network interface means including:

A. a plurality of receive circuit means each connected to another processing element via a receive line, each including;

i. receive shift register means for sequentially receiving and storing serial message signals during a message transfer interval,

ii. error checking means connected to said receive shift register means for generating a receive acknowledgement signal in response to the correct receipt of said message,

iii. acknowledgement signal receiving means for receiving, during an acknowledgement signal transfer interval, an acknowledgement signal from the error checking means of the connected processing element,

iv. receiver coupling means connected to said receive shift register means, said acknowledgement signal receiving means and said receive line for selectively coupling signals from said receive line to said receive shift register means during said message transfer interval and to said acknowledgement signal receiving means during said acknowledgement signal transfer interval, and

v. receive message storage means connected to said error checking means and said receive shift register means for retrieving a message stored in said receive shift register means in response to a determination by said error checking means that said message was correctly received;

B. a plurality of transmit circuit means each connected to another processing element via a transmit line, each including;

i. transmit message storage means for storing a message,

ii. transmit shift register means connected to said transmit message storage means for retrieving a message from said transmit message storage means and sequentially transmitting serial message signals during said message transfer interval,

iii. transmitter coupling means connected to said transmit shift register means, said error checking means, and said transmit line for selectively coupling signals onto said transmit line from said transmit shift register means during said message transfer interval and to said error checking means during said acknowledgement signal transfer interval;

C. transfer means for coupling the message signals of each received message from any one of said receive message storage means to any one of said transmit message storage means in response to the contents of a destination address field comprising;

i. switch means for controllably coupling the message signals received in any one of said receive message storage means to any one of said transmit storage means,

ii. routing circuit control means connected to said switch means, each of said receive circuit means, and to each of said receiver and transmitter coupling means, said routing circuit control means including means for (a) storing a correspondence between a destination address and one of said transmit circuit means, (b) reading the destination address field from a message, (c) identifying, in response to the destination address field of said message, a corresponding one of said transmit circuit means, and then enabling said switch means to couple all message signals of said message to said corresponding transmit circuit means, and (d) establishing said message transfer interval and said acknowledgment signal transfer interval by enabling said receiver and transmitter coupling means to respectively couple to said acknowledgement signal receiving means and said error checking means, and then to said receive and transmit shift register means.