Silicon wafers containing conductive feedthroughs

• US 5,166,097 A
• Filed: 11/26/1990
• Issued: 11/24/1992
• Est. Priority Date: 11/26/1990
• Status: Expired due to Term

• Current Assignee: The Boeing Co.
• Original Assignee: The Boeing Co.
• Inventors: Tanielian, Minas H.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): HOLTZMAN, LAURA
• Application Number:
  US07/618,056
• Time in Patent Office: 729 Days
• Field of Search: 437/195, 437/203, 437/915
• US Class Current: 438/667
• CPC Class Codes: H01L 21/30608 Anisotropic liquid etching H01L21/3063 takes precedence
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/473 by flowing liquids H01L23/4332, H01L23/4338 take precedence
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: Y10S 438/928 Front and rear surface processing

Abstract

Methods of forming electrically and/or thermally conductive feedthroughs in silicon wafers by etching a patterned silicon wafer, and formation of multichip modules utilizing silicon wafers having feedthroughs, are disclosed.

Claims

1. A method of forming electrically conductive feedthroughs in a silicon wafer, comprising:

providing a patterned silicon wafer;

anisotropically etching said wafer to produce a plurality of feedthroughs in said wafer, wherein said etching is carried out by a wet chemical etching technique applied simultaneously to both sides of said wafer, said both sides being patterned in substantially the same manner;

coating an area of said wafer containing said feedthroughs with a dielectric layer to provide electrical isolation between said feedthroughs and said wafer; and

metallizing said feedthroughs to thereby provide an electrical or thermal interconnection from one side of said wafer to the other.

2. The method of claim 1, wherein said wet chemical etching technique is carried out with aqueous alkali metal hydroxide.

3. The method of claim 1, wherein said etching is carried out at a temperature above room temperature.

4. The method of claim 1, wherein said dielectric layer is formed by oxidation of the silicon wafer or by deposition of silicon oxide or nitride on said wafer.

5. The method of claim 1, further comprising substantially filling said feedthroughs with a conductive metal paste and firing the paste to convert it to its metallic form.

6. The method of claim 1, wherein said feedthroughs are located in a peripheral region of said wafer that surrounds a central area of said wafer having no feedthroughs.

7. The method of claim 6, wherein said central area is sized to accommodate integrated circuitry.

8. The method of claim 6, further comprising etching away the central area of said wafer to thereby form a silicon wafer spacer.